The DRV871x-Q1 provides dedicated driver disable functions with the DRVOFF/nFLT pin and EN_DRV SPI register bit on SPI device variants. When DRVOFF/nFLT or EN_DRV are asserted, all half-bridges will be set Hi-Z by enabling the gate driver pull downs regardless of the other pin or SPI inputs.
The EN_DRV SPI register bit is provided for a controlled power up sequence. After device power up all the half-bridges remain disabled (all pulldowns active, EN_DRV = 0b) until the EN_DRV register bit is asserted high. This allows for the system to power up and conduct configuration sequences before the gate drivers are enabled. On H/W devices, this functionality is not provided and the driver will automatically enable after power up.
The DRVOFF/nFLT pin provides a direct hardware pin to shutdown the output drivers without relying on an SPI command or PWM input change.
The DRVOFF/nFLT pin is a multi-function configurable pin. By default, the pin functions as a global driver disable. If this function is not required, the pin be changed to an open-drain fault interrupt for the MCU through the device DRVOFF_nFLT register setting. When configured as DRVOFF, a logic high input will disable the drivers and logic low will allow for normal operation.