SLVSEA2B August   2020  – June 2021 DRV8714-Q1 , DRV8718-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 6.2 VQFN (RHA) 40-Pin Package and Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Device Interface Variants
        1. Serial Peripheral Interface (SPI)
        2. Hardware (H/W)
      3. 8.3.3 Input PWM Control Modes
        1. Half-Bridge Control Scheme With Input PWM Mapping
          1. DRV8718-Q1 Half-Bridge Control
          2. DRV8714-Q1 Half-Bridge Control
        2. H-Bridge Control
          1. DRV8714-Q1 H-Bridge Control
        3. Split HS and LS Solenoid Control
          1. DRV8714-Q1 Split HS and LS Solenoid Control
      4. 8.3.4 Smart Gate Driver
        1. Functional Block Diagram
        2. Slew Rate Control (IDRIVE)
        3. Gate Drive State Machine (TDRIVE)
        4. Propagation Delay Reduction (PDR)
          1. PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. PDR Pre-Charge/Pre-Discharge Setup
          2. PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. PDR Post-Charge/Post-Discharge Setup
          3. Detecting Drive and Freewheel MOSFET
        5. Automatic Duty Cycle Compensation (DCC)
        6. Closed Loop Slew Time Control (STC)
          1. STC Control Loop Setup
      5. 8.3.5 Tripler (Dual-Stage) Charge Pump
      6. 8.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 8.3.7 Pin Diagrams
        1. Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. Logic Level Push Pull Output (SDO)
        3. Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. Quad-Level Input (GAIN, MODE)
        5. Six-Level Input (IDRIVE, VDS)
      8. 8.3.8 Protection and Diagnostics
        1.  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2.  Low IQ Powered Off Braking (POB, BRAKE)
        3.  Fault Reset (CLR_FLT)
        4.  DVDD Logic Supply Power on Reset (DVDD_POR)
        5.  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6.  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7.  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8.  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9.  Gate Driver Fault (VGS_GDF)
        10. Thermal Warning (OTW)
        11. Thermal Shutdown (OTSD)
        12. Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. Watchdog Timer
        14. Fault Detection and Response Summary Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inactive or Sleep State
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Maps
      1. 8.6.1 DRV8718-Q1 Register Map
      2. 8.6.2 DRV8714-Q1 Register Map
      3. 8.6.3 DRV8718-Q1 Register Descriptions
        1. DRV8718-Q1_STATUS Registers
        2. DRV8718-Q1_CONTROL Registers
        3. DRV8718-Q1_CONTROL_ADV Registers
        4. DRV8718-Q1_STATUS_ADV Registers
      4. 8.6.4 DRV8714-Q1 Register Descriptions
        1. DRV8714-Q1_STATUS Registers
        2. DRV8714-Q1_CONTROL Registers
        3. DRV8714-Q1_CONTROL_ADV Registers
        4. DRV8714-Q1_STATUS_ADV Registers
  9. Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Gate Driver Configuration
          1. VCP Load Calculation Example
          2. IDRIVE Calculation Example
          3. tDRIVE Calculation Example
          4. Maximum PWM Switching Frequency
        2. Current Shunt Amplifier Configuration
        3. Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device Documentation and Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Low IQ Powered Off Braking (POB, BRAKE)

The DRV871x-Q1 provide the ability to enable the low-side gate drivers while the device is in its low-power sleep mode (nSLEEP = logic low). This allows the external low-side power MOSFETs to be enabled while maintaining a low quiescent current draw from the power supply. Enabling the external low-side MOSFETs allows the device to actively brake a motor connected to the external half-bridges by shorting the back emf across the motor terminals. This can help prevent reverse driving of the motor by an external force from overcharging the system power supply by dissipating the energy in the low-side MOSFETs. This function is only available while the device is in its low-power sleep mode. The function is enabled by taking the BRAKE pin to logic high.

The powered off braking function is available on half-bridges 5, 6, 7, and 8 on the DRV8718-Q1 device. On the DRV8714-Q1, the power off braking function is available on all four half-bridges. The BRAKE pin will enable or disable the low-side gate drivers for all four of the half-bridges together. The powered off braking function requires the PVDD voltage supply to be present in order to enable the low-side gate drivers, but the function can operate without the DVDD logic power supply present.

In case of a short circuit to power supply fault present on the power stage, a simple overcurrent detector circuit with analog RC deglitch filter is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the device low-power sleep mode. The overcurrent comparator and RC deglitch filter values are fixed and cannot be adjusted.

The powered off braking function is enabled through the BRAKE pin and the BRAKE pin can be pulled high through several different methods. To reduce quiescent current draw, the pulldown resistance of the BRAKE pin is reduced to 1MOhm while in device low-power sleep mode. The BRAKE pin can be always left high while the device is in low-power sleep mode or can be set high in response to a rising voltage on the power supply. The BRAKE pin has an internal voltage clamp allowing it to be connected directly to the PVDD battery supply through a Zener diode (to set overvoltage threshold) with a series resistor to limit the current. The powered off function can be set to automatically enable in low-power sleep mode by leaving the BRAKE pin disconnected and relying on the internal overvoltage monitor.

Some methods to pull up the BRAKE pin and enable the powered off braking function include:

  • Option 1: Internal overvoltage monitor. BRAKE pin should be left not-connected (Hi-Z)
  • Option 2: Voltage triggered pull up with passive Zener diode. An external Zener diode can be added to the BRAKE pin to create an overvoltage trigger that is lower than the internal overvoltage monitor.
  • Option 3: MCU fixed digital output high or MCU digital output in response to motor movement detected by senor or rising voltage. A digital output to the BRAKE pin can directly control whether the power off braking function is enabled (LO = disabled, HI = enabled).
  • Option 4: The power off braking function can be disabled by shorting/connecting the BRAKE pin directly to PCB ground.

By default (BRAKE pin not connected), the powered off braking function is enabled by an internal overvoltage monitor that will detect the PVDD voltage and enable the low-side braking if voltage crosses the comparator threshold. The internal overvoltage monitor and power off braking function can be disabled by shorting the BRAKE pin directly to PCB ground.

GUID-533C8BBC-CFA7-40B4-8BFF-0183E893545B-low.gifFigure 8-28 Powered Off Braking

If the powered off braking function is not utilized, the BRAKE pin should be connected directly to GND.