SLVSEA2B August   2020  – June 2021 DRV8714-Q1 , DRV8718-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 6.2 VQFN (RHA) 40-Pin Package and Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Device Interface Variants
        1. 8.3.2.1 Serial Peripheral Interface (SPI)
        2. 8.3.2.2 Hardware (H/W)
      3. 8.3.3 Input PWM Control Modes
        1. 8.3.3.1 Half-Bridge Control Scheme With Input PWM Mapping
          1. 8.3.3.1.1 DRV8718-Q1 Half-Bridge Control
          2. 8.3.3.1.2 DRV8714-Q1 Half-Bridge Control
        2. 8.3.3.2 H-Bridge Control
          1. 8.3.3.2.1 DRV8714-Q1 H-Bridge Control
        3. 8.3.3.3 Split HS and LS Solenoid Control
          1. 8.3.3.3.1 DRV8714-Q1 Split HS and LS Solenoid Control
      4. 8.3.4 Smart Gate Driver
        1. 8.3.4.1 Functional Block Diagram
        2. 8.3.4.2 Slew Rate Control (IDRIVE)
        3. 8.3.4.3 Gate Drive State Machine (TDRIVE)
        4. 8.3.4.4 Propagation Delay Reduction (PDR)
          1. 8.3.4.4.1 PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 8.3.4.4.1.1 PDR Pre-Charge/Pre-Discharge Setup
          2. 8.3.4.4.2 PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 8.3.4.4.2.1 PDR Post-Charge/Post-Discharge Setup
          3. 8.3.4.4.3 Detecting Drive and Freewheel MOSFET
        5. 8.3.4.5 Automatic Duty Cycle Compensation (DCC)
        6. 8.3.4.6 Closed Loop Slew Time Control (STC)
          1. 8.3.4.6.1 STC Control Loop Setup
      5. 8.3.5 Tripler (Dual-Stage) Charge Pump
      6. 8.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 8.3.7 Pin Diagrams
        1. 8.3.7.1 Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. 8.3.7.2 Logic Level Push Pull Output (SDO)
        3. 8.3.7.3 Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. 8.3.7.4 Quad-Level Input (GAIN, MODE)
        5. 8.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 8.3.8 Protection and Diagnostics
        1. 8.3.8.1  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2. 8.3.8.2  Low IQ Powered Off Braking (POB, BRAKE)
        3. 8.3.8.3  Fault Reset (CLR_FLT)
        4. 8.3.8.4  DVDD Logic Supply Power on Reset (DVDD_POR)
        5. 8.3.8.5  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6. 8.3.8.6  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7. 8.3.8.7  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8. 8.3.8.8  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9. 8.3.8.9  Gate Driver Fault (VGS_GDF)
        10. 8.3.8.10 Thermal Warning (OTW)
        11. 8.3.8.11 Thermal Shutdown (OTSD)
        12. 8.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. 8.3.8.13 Watchdog Timer
        14. 8.3.8.14 Fault Detection and Response Summary Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inactive or Sleep State
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. 8.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Maps
      1. 8.6.1 DRV8718-Q1 Register Map
      2. 8.6.2 DRV8714-Q1 Register Map
      3. 8.6.3 DRV8718-Q1 Register Descriptions
        1. 8.6.3.1 DRV8718-Q1_STATUS Registers
        2. 8.6.3.2 DRV8718-Q1_CONTROL Registers
        3. 8.6.3.3 DRV8718-Q1_CONTROL_ADV Registers
        4. 8.6.3.4 DRV8718-Q1_STATUS_ADV Registers
      4. 8.6.4 DRV8714-Q1 Register Descriptions
        1. 8.6.4.1 DRV8714-Q1_STATUS Registers
        2. 8.6.4.2 DRV8714-Q1_CONTROL Registers
        3. 8.6.4.3 DRV8714-Q1_CONTROL_ADV Registers
        4. 8.6.4.4 DRV8714-Q1_STATUS_ADV Registers
  9. Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Gate Driver Configuration
          1. 9.2.2.1.1 VCP Load Calculation Example
          2. 9.2.2.1.2 IDRIVE Calculation Example
          3. 9.2.2.1.3 tDRIVE Calculation Example
          4. 9.2.2.1.4 Maximum PWM Switching Frequency
        2. 9.2.2.2 Current Shunt Amplifier Configuration
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device Documentation and Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Wide Common-Mode Current Shunt Amplifiers

The DRV871x-Q1 integrates two high-performance, wide common-mode, bidirectional, current-shunt amplifiers for current measurements using shunt resistors in the external half-bridges. Current measurements are commonly used to implement overcurrent protection, external torque control, or commutation with an external controller. Due to the high common-mode range of the shunt amplifier it can support low-side, high-side, or inline shunt configurations. The current shunt amplifiers include features such as programmable gain, unidirectional and bidirectional support, output blanking, and a dedicated voltage reference pin (AREF) to set a mid point bias voltage for the amplifier output. A simplified block diagram is shown in Figure 8-17. SPx should connect to the positive terminal of the shunt resistor and SNx should connect to the negative terminal of the shunt resistor. If the amplifiers are not utilized, the AREF, SNx, SPx inputs can be tied to AGND, AGND to PCB GND and the SOx outputs left floating.

Note: It should be noted that in high-side sense configuration there exists a leakage path of approximately 600kΩ to GND when nSLEEP = 0V.
GUID-713838A6-8588-4A66-9034-811571A270B4-low.gif Figure 8-17 Amplifier Simplified Block Diagram

A detailed block diagram is shown in Figure 8-18. The wide common mode amplifier is implemented with a two stage differential architecture. The 1st differential stage supports a wide common mode input, differential output, and has a fixed gain, G = 2. The 2nd differential stage supports a variable gain adjustment, G = 5, 10, 20, or 40. The total gain of the two stages will be G = 10, 20, 40, or 80.

The amplifier can also generate an output voltage bias through the AREF pin. The AREF pin goes to a divider network, a buffer, and then sets the output voltage bias for the differential amplifier. On SPI device variants, the gain is configured through the register setting CSA_GAIN and the reference division ratio through CSA_DIV. On H/W device variants, the reference division ratio is fixed to VAREF / 2. The gain is configured through the GAIN pin.

GUID-EC6EAB99-6C42-4DE6-84DE-AC0EB98F3ADE-low.gif Figure 8-18 Amplifier Detailed Block Diagram
GUID-3467F9F8-F114-4AAB-99A6-FE7E5A7FCA62-low.gifFigure 8-19 Shared Shunt Resistor
GUID-068B1B0C-5B9E-4880-8C0B-5877BE910351-low.gifFigure 8-20 Individual H-Bridge Shunt Resistor

The DRV8718-Q1 inline shunt amplifier can be used to continuously sense motor current even in shared group or zone control configurations. The DRV8714-Q1 provides two shunt amplifiers for the four half-bridge gate drivers allowing for individual H-bridge current sensing if the system requires.

Lastly, the amplifier has an output blanking switch. This option is only available on SPI device variants. The output switch can be used to disconnect the amplifier output during PWM switching to reduce output noise (blanking). The blanking circuit can be set trigger on the active half-bridge (half-bridge 1-8) through the CSA_BLK_SEL_x register setting. The blanking period can be configured through the CSA_BLK_x register setting. If the gate drivers are transitioning between high-side and low-side FET turn on and turn off or vice versa, the blanking time will extend through the dead-time window to avoid amplifier signal noise if the output swings or noise couples during the dead-time period. An output hold up capacitor is recommended to stabilize the amplifier output when it is disconnected during blanking. Typically this capacitor should be after a series resistor in a RC filter configuration to limit direct capacitance seen directly at the amplifier output. An example of the blanking function is shown in Figure 8-21.

GUID-96CDD1BA-EB44-4841-87FA-58192EAF1E01-low.gif Figure 8-21 Amplifier Blanking Example