If the VGS voltage does not cross the the VGS_LVL comparator level for longer than the tDRIVE time, the DRV871x-Q1 detects a VGS gate fault condition. Additionally, in independent half-bridge and DRV8714-Q1 split HS/LS PWM control (BRG_MODE = 00b, 11b) the device can be configured to disable all half-bridges or only the associated half-bridge in which the gate fault occurred through the VGS_IND register setting. In the DRV8714-Q1 PH/EN and PWM H-bridge control modes (BRG_MODE = 01b, 10b), the VGS_IND register setting can be used to disable all H-bridges or only the associated H-bridge in which the fault occurred.
On SPI device variants, the VGS gate fault monitor can respond and recover in four different modes set through the VGS_MODE register setting.
On H/W device variants, the VGS gate fault mode is fixed to cycle by cycle and tDRIVE is fixed to 4 µs. Independent half-bridge shutdown is automatically enabled for the independent half-bridge and split HS/LS PWM control modes. Independent H-bridge shutdown is automatically enabled for the H-bridge PWM control modes. Additionally, the VGS gate fault protection can be disabled through level 6 of the VDS pin multi-level input.