SLVSEA2B August   2020  – June 2021 DRV8714-Q1 , DRV8718-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 6.2 VQFN (RHA) 40-Pin Package and Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Device Interface Variants
        1. 8.3.2.1 Serial Peripheral Interface (SPI)
        2. 8.3.2.2 Hardware (H/W)
      3. 8.3.3 Input PWM Control Modes
        1. 8.3.3.1 Half-Bridge Control Scheme With Input PWM Mapping
          1. 8.3.3.1.1 DRV8718-Q1 Half-Bridge Control
          2. 8.3.3.1.2 DRV8714-Q1 Half-Bridge Control
        2. 8.3.3.2 H-Bridge Control
          1. 8.3.3.2.1 DRV8714-Q1 H-Bridge Control
        3. 8.3.3.3 Split HS and LS Solenoid Control
          1. 8.3.3.3.1 DRV8714-Q1 Split HS and LS Solenoid Control
      4. 8.3.4 Smart Gate Driver
        1. 8.3.4.1 Functional Block Diagram
        2. 8.3.4.2 Slew Rate Control (IDRIVE)
        3. 8.3.4.3 Gate Drive State Machine (TDRIVE)
        4. 8.3.4.4 Propagation Delay Reduction (PDR)
          1. 8.3.4.4.1 PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 8.3.4.4.1.1 PDR Pre-Charge/Pre-Discharge Setup
          2. 8.3.4.4.2 PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 8.3.4.4.2.1 PDR Post-Charge/Post-Discharge Setup
          3. 8.3.4.4.3 Detecting Drive and Freewheel MOSFET
        5. 8.3.4.5 Automatic Duty Cycle Compensation (DCC)
        6. 8.3.4.6 Closed Loop Slew Time Control (STC)
          1. 8.3.4.6.1 STC Control Loop Setup
      5. 8.3.5 Tripler (Dual-Stage) Charge Pump
      6. 8.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 8.3.7 Pin Diagrams
        1. 8.3.7.1 Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. 8.3.7.2 Logic Level Push Pull Output (SDO)
        3. 8.3.7.3 Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. 8.3.7.4 Quad-Level Input (GAIN, MODE)
        5. 8.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 8.3.8 Protection and Diagnostics
        1. 8.3.8.1  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2. 8.3.8.2  Low IQ Powered Off Braking (POB, BRAKE)
        3. 8.3.8.3  Fault Reset (CLR_FLT)
        4. 8.3.8.4  DVDD Logic Supply Power on Reset (DVDD_POR)
        5. 8.3.8.5  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6. 8.3.8.6  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7. 8.3.8.7  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8. 8.3.8.8  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9. 8.3.8.9  Gate Driver Fault (VGS_GDF)
        10. 8.3.8.10 Thermal Warning (OTW)
        11. 8.3.8.11 Thermal Shutdown (OTSD)
        12. 8.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. 8.3.8.13 Watchdog Timer
        14. 8.3.8.14 Fault Detection and Response Summary Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inactive or Sleep State
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. 8.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Maps
      1. 8.6.1 DRV8718-Q1 Register Map
      2. 8.6.2 DRV8714-Q1 Register Map
      3. 8.6.3 DRV8718-Q1 Register Descriptions
        1. 8.6.3.1 DRV8718-Q1_STATUS Registers
        2. 8.6.3.2 DRV8718-Q1_CONTROL Registers
        3. 8.6.3.3 DRV8718-Q1_CONTROL_ADV Registers
        4. 8.6.3.4 DRV8718-Q1_STATUS_ADV Registers
      4. 8.6.4 DRV8714-Q1 Register Descriptions
        1. 8.6.4.1 DRV8714-Q1_STATUS Registers
        2. 8.6.4.2 DRV8714-Q1_CONTROL Registers
        3. 8.6.4.3 DRV8714-Q1_CONTROL_ADV Registers
        4. 8.6.4.4 DRV8714-Q1_STATUS_ADV Registers
  9. Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Gate Driver Configuration
          1. 9.2.2.1.1 VCP Load Calculation Example
          2. 9.2.2.1.2 IDRIVE Calculation Example
          3. 9.2.2.1.3 tDRIVE Calculation Example
          4. 9.2.2.1.4 Maximum PWM Switching Frequency
        2. 9.2.2.2 Current Shunt Amplifier Configuration
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device Documentation and Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

4.9 V ≤ VPVDD ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V and TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (DRAIN, DVDD, PVDD, VCP)
IPVDDQ PVDD sleep mode current VPVDD, VDRAIN = 13.5 V, nSLEEP = 0 V
BRAKE = 0 V, –40 ≤ TJ ≤ 85°C
2.25 3.5 µA
VPVDD, VDRAIN = 13.5 V, nSLEEP = 0 V
BRAKE = 5 V, –40 ≤ TJ ≤ 85°C
10 15 µA
IDRAINQ DRAIN sleep mode current VPVDD, VDRAIN = 13.5 V, nSLEEP = 0 V
–40 ≤ TJ ≤ 85°C
1.25 2 µA
IDVDDQ DVDD sleep mode current VPVDD, VDRAIN = 13.5 V, nSLEEP = 0 V
–40 ≤ TJ ≤ 85°C
1.25 3 µA
VPVDD, VDRAIN = 13.5 V, nSLEEP = 0 V
–40 ≤ TJ ≤ 85°C, DRV8714-Q1 RHA
2.25 5.25
IPVDD PVDD active mode current VPVDD, VDRAIN = 13.5 V, nSLEEP = 5 V 13.5 15.5 mA
IDRAIN DRAIN active mode current VPVDD, VDRAIN = 13.5 V, nSLEEP = 5 V, VDS_LVL  ≤ 500 mV 1 1.65 mA
IDVDD DVDD active mode current VDVDD = 5 V, SDO = 0 V
DRV8718-Q1 RVJ, DRV8714-Q1 RVJ
8 10 mA
VDVDD = 5 V, SDO = 0 V
DRV8714-Q1 RHA
10 13 mA
fDVDD Digital oscilator switching frequency Primary frequency of spread spectrum. 14.25 MHz
tWAKE Turnon time nSLEEP = 5 V to active mode 1 ms
tSLEEP Turnoff time nSLEEP = 0 V to sleep mode 1 ms
VVCP Charge pump regulator voltage with respect to PVDD
Triple mode
VPVDD ≥ 9 V, IVCP ≤ 30 mA 9.5 10.5 11 V
VPVDD = 7 V, IVCP ≤ 25 mA 8.5 9 11
VPVDD = 7 V, IVCP ≤ 25 mA,
DRV8714-Q1 RHA
8.4 9 11
VPVDD = 4.9 V, IVCP ≤ 12 mA 7 7.5 11
VPVDD = 4.9 V, IVCP ≤ 12 mA,
DRV8714-Q1 RHA
6.8 7.5 11
Charge pump regulator voltage with respect to PVDD
Double mode
VPVDD ≥ 13 V, IVCP ≤ 25 mA 9.5 10.5 11 V
VPVDD = 9 V, IVCP ≤ 13.5 mA 7 8 11
VPVDD = 9 V, IVCP ≤ 13.5 mA,
DRV8714-Q1 RHA
6.9 8 11
VPVDD = 7 V, IVCP ≤ 10 mA 5.4 6 11
VPVDD = 7 V, IVCP ≤ 10 mA,
DRV8714-Q1 RHA
5.3 6 11
fVCP Charge pump switching frequency Primary frequency of spread spectrum. 400 kHz
LOGIC-LEVEL INPUTS (BRAKE, DRVOFF/nFLT, INx/EN, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
VIL Input logic low voltage DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI 0 VDVDD x 0.3 V
BRAKE 0 0.6
VIH Input logic high voltage DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI VDVDD x 0.7 5.5 V
BRAKE 1.8 5.5
VHYS Input hysteresis DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI VDVDD x 0.1 V
BRAKE 0.5
IIL Input logic low current VDIN = 0 V, BRAKE, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI –5 5 µA
VDIN = 0 V, nSCS 50 100
IIH Input logic high current VDIN = 5 V, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI 50 100 µA
VDIN = 5 V, VDVDD = 5 V, nSCS –5 5
VDIN = 5 V, nSLEEP = 0V, BRAKE 5 10 µA
VDIN = 5 V, nSLEEP = 5V, BRAKE 35 100 µA
RPD Input pulldown resistance To GND, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI 50 100 150
BRAKE to GND, nSLEEP = 0 V
BRAKE ≤ 2 V, 4.9 V ≤ VPVDD ≤ VPOB_OV
500 1000 1500
BRAKE to GND, nSLEEP = 5 V
BRAKE ≤ 2 V, 4.9 V ≤ VPVDD ≤ VPOB_OV
50 136 200
RPU Input pullup resistance To DVDD, nSCS 50 100 150
MULTI-LEVEL INPUTS (GAIN, IDRIVE, MODE, VDS)
VQI1 Quad-level input 1 GAIN, MODE
Voltage to set level 1
0 VDVDD x 0.1 V
RQI2 Quad-level input 2 GAIN, MODE
Resistance to GND to set level 2
44.65 47 49.35
RQI3 Quad-level input 3 GAIN, MODE
Resistance to GND to set level 3
500 Hi-Z
VQI4 Quad-level input 4 GAIN, MODE
Voltage to set level 4
VDVDD x 0.9 5.5 V
RQPD Quad-level pulldown resistane To GND, GAIN, MODE 98
RQPU Quad-level pullup resistane To DVDD, GAIN, MODE 98
VSI1 Six-level input 1 IDRIVE, VDS
Voltage to set level 1
0 VDVDD x 0.1 V
RSI2 Six-level input 2 IDRIVE, VDS
Resistance to GND to set level 2
28.5 30 31.5
RSI3 Six-level input 3 IDRIVE, VDS
Resistance to GND to set level 3
95 100 105
RSI4 Six-level input 4 IDRIVE, VDS
Resistance to GND to set level 4
500 Hi-Z
RSI5 Six-level input 5 IDRIVE, VDS
Resistance to DVDD to set level 5
58.9 62 65.1
RSI6 Six-level input 6 IDRIVE, VDS
Voltage to set level 6
VDVDD x 0.9 5.5 V
RSPD Six-level pulldown resistane To GND, IDRIVE, VDS 98
RSPU Six-level pullup resistane To DVDD, IDRIVE, VDS 69
LOGIC-LEVEL OUTPUTS (DRVOFF/nFLT, SDO)
VOL Output logic low voltage IDOUT = 5 mA 0.5 V
VOH Output logic high voltage IDOUT = –5 mA, SDO VDVDD x 0.8 V
IODZ Open-drain logic high current VOD = 5 V, DRVOFF/nFLT –10 10 µA
GATE DRIVERS (GHx, GLx)
VGHx_L GHx low level output voltage IDRVN_HS = ISTRONG, IGHx = 1mA,
GHx to SHx
0 0.25 V
VGLx_L GLx low level output voltage IDRVN_LS = ISTRONG, IGLx = 1mA,
GLx to PGNDx
0 0.25 V
VGHx_H GHx high level output voltage IDRVP_HS = IHOLD, IGHx = 1mA,
VCP to GHx
0 0.25 V
VGLx_H GLx high level output voltage IDRVP_LS = IHOLD, IGLx = 1mA,
GLx to PGNDx
10.5 12.5 V
IDRVP, SPI Peak gate current (source)
SPI Device
IDRVP_x = 0000b, VGSx = 3 V 0.2 0.5 0.83 mA
IDRVP_x = 0001b, VGSx = 3 V 0.5 1 1.6
IDRVP_x = 0010b, VGSx = 3 V 1.3 2 2.8
IDRVP_x = 0011b, VGSx = 3 V 2.1 3 4
IDRVP_x = 0100b, VGSx = 3 V 2.9 4 5.3
IDRVP_x = 0101b, VGSx = 3 V 3.75 5 6.4
IDRVP_x = 0110b, VGSx = 3 V 4.5 6 7.6
IDRVP_x = 0111b, VGSx = 3 V 5.5 7 9
IDRVP_x = 1000b, VGSx = 3 V 6 8 10
IDRVP_x = 1001b, VGSx = 3 V 9 12 15
IDRVP_x = 1010b, VGSx = 3 V 12 16 20
IDRVP_x = 1011b, VGSx = 3 V 15 20 25
IDRVP_x = 1100b, VGSx = 3 V 18 24 30
IDRVP_x = 1101b, VGSx = 3 V 24 31 40
IDRVP_x = 1110b, VGSx = 3 V 28 48 62
IDRVP_x = 1111b, VGSx = 3 V 46 62 78
IDRVP, H/W Peak gate current (source)
H/W Device
IDRIVE six-level 1, VGSx = 3 V 0.2 1 1.6 mA
IDRIVE six-level 2, VGSx = 3 V 2.9 4 5.3
IDRIVE six-level 3, VGSx = 3 V 6 8 10
IDRIVE six-level 4, VGSx = 3 V 12 16 20
IDRIVE six-level 5, VGSx = 3 V 24 31 40
IDRIVE six-level 6, VGSx = 3 V 46 62 78
IDRVN, SPI Peak gate current (sink)
SPI Device
IDRVN_x = 0000b, VGSx = 3 V 0.07 0.5 0.85 mA
IDRVN_x = 0001b, VGSx = 3 V 0.23 1 1.7
IDRVN_x = 0010b, VGSx = 3 V 0.7 2 3.2
IDRVN_x = 0011b, VGSx = 3 V 1.2 3 4.6
IDRVN_x = 0100b, VGSx = 3 V 1.75 4 5.9
IDRVN_x = 0101b, VGSx = 3 V 2.4 5 7.2
IDRVN_x = 0110b, VGSx = 3 V 3 6 8.5
IDRVN_x = 0111b, VGSx = 3 V 3.6 7 9.8
IDRVN_x = 1000b, VGSx = 3 V 4.3 8 11
IDRVN_x = 1001b, VGSx = 3 V 7.3 12 16
IDRVN_x = 1010b, VGSx = 3 V 11 16 20
IDRVN_x = 1011b, VGSx = 3 V 14.3 20 25
IDRVN_x = 1100b, VGSx = 3 V 18 24 30
IDRVN_x = 1101b, VGSx = 3 V 24 31 40
IDRVN_x = 1110b, VGSx = 3 V 28 48 62
IDRVN_x = 1111b, VGSx = 3 V 46 62 78
IDRVN, H/W Peak gate current (sink)
H/W Device
IDRIVE six-level 1, VGSx = 3 V 0.23 1 1.7 mA
IDRIVE six-level 2, VGSx = 3 V 1.75 4 5.9
IDRIVE six-level 3, VGSx = 3 V 4.3 8 11
IDRIVE six-level 4, VGSx = 3 V 11 16 20
IDRIVE six-level 5, VGSx = 3 V 24 31 40
IDRIVE six-level 6, VGSx = 3 V 46 62 78
IHOLD Gate pullup hold current Gate hold source current, VGSx = 3 V 5 16 30 mA
ISTRONG Gate pulldown strong current Gate strong pulldown current, VGSx = 3 V
IDRV = 0.5 to 12mA 
30 62 100 mA
Gate strong pulldown current, VGSx = 3 V
IDRV = 16 to 62mA 
45 128 205
RPDSA_LS Low-side semi-active gate pulldown GLx to PGNDx, VGSx = 3 V 1.8 kΩ
GLx to PGNDx, VGSx = 1 V 5 kΩ
RPD_HS High-side passive gate pulldown resistor GHx to SHx 150 kΩ
RPD_LS Low-side passive gate pulldown resistor DRV8718-Q1, GL1, GL2, GL3, and GL4 to PGND1 150 kΩ
ISHx Switch-node sense leakage current Into SHx, SHx = DRAIN ≤ 28 V
GHx – SHx = 0 V, nSLEEP = 0 V
–5 0 20 µA
Into SHx, SHx = DRAIN ≤ 37 V
GHx – SHx = 0 V, nSLEEP = 0 V
–5 0 80 µA
Into SHx, SHx = DRAIN ≤ 37 V
GHx – SHx = 0 V, nSLEEP = 5 V
–150 –100 0 µA
GATE DRIVER TIMINGS (GHx, GLx)
tPDR_LS Low-side rising propagation delay Input to GLx rising 300 850 ns
tPDF_LS Low-side falling propagation delay Input to GLx falling 300 600 ns
tPDR_HS High-side rising propagation delay Input to GHx rising 300 600 ns
tPDF_HS High-side falling propagation delay Input to GHx falling 300 600 ns
tDEAD Internal handshake dead-time GLx/GHx falling 10% to GHx/GLx rising 10% 350 ns
tDEAD_D, SPI Insertable digital dead-time
SPI Device
VGS_TDEAD = 00b, Handshake only 0 µs
VGS_TDEAD = 01b 1.6 2 2.4
VGS_TDEAD = 10b 3.4 4 4.6
VGS_TDEAD = 11b 7.2 8 8.8
tDEAD_D, H/W Insertable digital dead-time
H/W Device
Handshake only 0 µs
CURRENT SHUNT AMPLIFIERS (AREF, SNx, SOx, SPx)
VCOM Common mode input range –2 VPVDD + 2 V
GCSA, SPI Sense amplifier gain
SPI device
CSA_GAIN = 00b 9.75 10 10.25 V/V
CSA_GAIN = 01b 19.5 20 20.5
CSA_GAIN = 10b 39 40 41
CSA_GAIN = 11b 78 80 82
GCSA, H/W Sense amplifier gain
H/W device
GAIN quad-level 1 9.75 10 10.25 V/V
GAIN quad-level 2 19.5 20 20.5
GAIN quad-level 3 39 40 41
GAIN quad-level 4 78 80 82
tSET Sense amplifier settling time to ±1% VSO_ STEP = 1.5 V, GCSA = 10 V/V
CSO = 60 pF
2.2 µs
VSO_ STEP = 1.5 V, GCSA = 20 V/V
CSO = 60 pF
2.2
VSO_ STEP = 1.5 V, GCSA = 40 V/V
CSO = 60 pF
2.2
VSO_ STEP = 1.5 V, GCSA = 80 V/V
CSO = 60 pF
3
tBLK, SPI Sense amplifier output blanking time
SPI Device
CSA_BLK = 000b, % of tDRIVE period 0 %
CSA_BLK = 001b, % of tDRIVE period 25
CSA_BLK = 010b, % of tDRIVE period 37.5
CSA_BLK = 011b, % of tDRIVE period 50
CSA_BLK = 100b, % of tDRIVE period 62.5
CSA_BLK = 101b, % of tDRIVE period 75
CSA_BLK = 110b, % of tDRIVE period 87.5
CSA_BLK = 111b, % of tDRIVE period 100
tBLK, H/W Sense amplifier output blanking time
H/W Device
0 ns
tSLEW Output slew rate CSO = 60 pF 2.5 V/µs
VBIAS, SPI Output voltage bias
SPI Device
VSPx = VSNx = 0 V, CSA_DIV = 0b VAREF / 2 V
VSPx = VSNx = 0 V, CSA_DIV = 1b VAREF / 8
VBIAS, H/W Output voltage bias
H/W Device
VAREF / 2 V
VLINEAR Linear output voltage range VAREF = 3.3 V = 5 V 0.25 VAREF – 0.25 V
VOFF Input offset voltage VSPx = VSNx = 0 V, TJ = 25℃ –1 1 mV
VOFF_D Input offset voltage drift VSPx = VSNx = 0 V ±10 ±25 µV/℃
IBIAS Input bias current VSPx = VSNx = 0 V 100 µA
IBIAS_OFF Input bias current offset ISPx – ISNx –1 1 µA
IAREF AREF input current VVREF = 3.3 V = 5 V
DRV8718-Q1 RVJ, DRV8714-Q1 RVJ
2 3 mA
CMRR Common mode rejection ratio DC, –40 ≤ TJ ≤ 125°C 72 90 dB
DC, –40 ≤ TJ ≤ 150°C 69 90
20kHz 80
PSRR Power supply rejection ratio PVDD to SOx, DC 100 dB
PVDD to SOx, 20kHz 90
PVDD to SOx, 400kHz 70
PROTECTION CIRCUITS
VPVDD_UV PVDD undervoltage threshold VPVDD rising 4.325 4.625 4.9 V
VPVDD falling 4.25 4.525 4.8
VPVDD_UV_HYS PVDD undervoltage hysteresis Rising to falling threshold 100 mV
tPVDD_UV_DG PVDD undervoltage deglitch time 8 10 12.75 µs
VPVDD_OV PVDD overvoltage threshold VPVDD rising, PVDD_OV_LVL = 0b 21 22.5 24 V
VPVDD falling, PVDD_OV_LVL = 0b 20 21.5 23
VPVDD falling, PVDD_OV_LVL = 0b, DRV8714-Q1 19.75 21.5 23
VPVDD rising, PVDD_OV_LVL = 1b 27 28.5 30
VPVDD falling, PVDD_OV_LVL = 1b 26 27.5 29
VPVDD falling, PVDD_OV_LVL = 1b, DRV8714-Q1 25.4 27.5 29
VPVDD_OV_HYS PVDD overvoltage hysteresis Rising to falling threshold 1 V
tPVDD_OV_DG PVDD overvoltage deglitch time PVDD_OV_DG = 00b 0.75 1 1.5 µs
PVDD_OV_DG = 01b 1.5 2 2.5
PVDD_OV_DG = 10b 3.25 4 4.75
PVDD_OV_DG = 11b 7 8 9
VDVDD_POR DVDD supply POR threshold DVDD falling 2.5 2.7 2.9 V
DVDD rising 2.6 2.8 3
VDVDD_POR_HYS DVDD POR hysteresis Rising to falling threshold 100 mV
tDVDD_POR_DG DVDD POR deglitch time 5 8 12.75 µs
VCP_UV, SPI Charge pump undervoltage threshold
SPI Device
VVCP - VPVDD, VVCP falling
VCP_UV = 0b
4 4.75 5.5 V
VVCP - VPVDD, VVCP falling
VCP_UV = 1b
5.5 6.25 7
VCP_UV, H/W Charge pump undervoltage threshold
H/W Device
4 4.75 5.5 V
tCP_UV_DG Charge pump undervoltage deglitch time 8 10 12.75 µs
VCP_SO Charge pump tripler to doubler switch over threshold VPVDD rising 18 18.75 19.5 V
VCP_SO Charge pump tripler to doubler switch over threshold VPVDD falling 17 17.75 18.5 V
tCP_SO_HYS Charge pump tripler to doubler switch over hysteresis 1 V
tCP_SO_DG Charge pump tripler to doubler switch over threshold deglitch 8 10 12.75 µs
VGS_CLP High-side driver VGS protection clamp 12.5 15 17 V
VGS_LVL Gate voltage monitor threshold
SPI Device
VGHx – VSHx, VGLx – VPGNDx
VGS_LVL = 0b
1.1 1.4 1.75 V
VGHx – VSHx, VGLx – VPGNDx 
VGS_LVL = 1b
0.75 1 1.2 V
Gate voltage monitor threshold
H/W Device
VGHx – VSHx, VGLx – VPGNDx 1.1 1.4 1.75 V
tGS_FLT_DG VGS fault monitor deglitch time 1.5 2 2.75 µs
tGS_HS_DG VGS handskahe monitor deglitch time 210 ns
tDRIVE, SPI VGS and VDS monitor blanking time
SPI Device
VGS_TDRV = 000b 1.5 2 2.5 µs
VGS_TDRV = 001b 3.25 4 4.75
VGS_TDRV = 010b 7.5 8 9
VGS_TDRV = 011b 10 12 14
VGS_TDRV = 100b 14 16 18
VGS_TDRV = 101b 20 24 28
VGS_TDRV = 110b 28 32 36
VGS_TDRV = 111b 80 96 120
tDRIVE, H/W VGS and VDS monitor blanking time
H/W Device
7.5 8 9 µs
VDS_LVL, SPI VDS overcurrent protection threshold
SPI Device
VDS_LVL = 0000b 0.04 0.06 0.08 V
VDS_LVL = 0001b 0.06 0.08 0.10
VDS_LVL = 0010b 0.075 0.10 0.125
VDS_LVL = 0011b 0.095 0.12 0.145
VDS_LVL = 0100b 0.11 0.14 0.17
VDS_LVL = 0101b 0.13 0.16 0.19
VDS_LVL = 0110b 0.15 0.18 0.21
VDS_LVL = 0111b 0.17 0.2 0.23
VDS_LVL = 1000b 0.255 0.3 0.345
VDS_LVL = 1001b 0.35 0.4 0.45
VDS_LVL = 1010b 0.44 0.5 0.56
VDS_LVL = 1011b 0.52 0.6 0.68
VDS_LVL = 1100b 0.61 0.7 0.79
VDS_LVL = 1101b 0.88 1 1.12
VDS_LVL = 1110b 1.2 1.4 1.6
VDS_LVL = 1111b 1.75 2 2.25
VDS_LVL, H/W VDS overcurrent protection threshold
H/W Device
VDS six-level input 1 0.04 0.06 0.08 V
VDS six-level input 2 0.075 0.10 0.125
VDS six-level input 3 0.17 0.2 0.23
VDS six-level input 4 0.44 0.5 0.56
VDS six-level input 5 0.88 1 1.12
VDS six-level input 6 Disabled
tDS_DG, SPI VDS overcurrent protection deglitch time
SPI Device
VDS_DG = 00b(1) 0.75 1 1.5 µs
VDS_DG = 01b 1.5 2 2.5
VDS_DG = 10b 3.25 4 4.75
VDS_DG = 11b 7.5 8 9
tDS_DG, H/W VDS overcurrent protection deglitch time
H/W Device
3.25 4 4.75 µs
IOLD Offline diagnostic current source Pull up current 3 mA
Pull down current 3
ROLD Offline open load resistance detection threshold VDS_LVL = 1.4 V,
4.9 V ≤ VDRAIN ≤ 18 V
22 50 kΩ
VDS_LVL = 1.4 V,
4.9 V ≤ VDRAIN ≤ 37 V
22 105 kΩ
VDS_LVL = 2 V,
4.9 V ≤ VDRAIN ≤ 18 V
10 25 kΩ
VDS_LVL = 2 V,
4.9 V ≤ VDRAIN ≤ 37 V
10 50 kΩ
tWD Watchdog timer period WD_WIN = 0b 36 40 44 ms
WD_WIN = 1b 90 100 110
VPOB_OV Power off braking overvoltage threshold Rising 28 30.5 33 V
Falling 25 27 29.5 V
VPOB_OV_HYS Power off braking overvoltage hysteresis 3 V
IPOB_P Power off braking gate source current 15 mA
IPOB_N Power off braking gate sink current 27 mA
VPOB Power off braking gate pull up voltage VPVDD ≥ 8V 5.5 12.5 V
tPOB_ON Power off braking turn-on time 13 µs
tPOB_OFF Power off braking turn-off time 2.5 µs
VPOB_VDS Power off braking VDS comparator threshold Rising 250 350 450 mV
tPOB_VDS Power off braking VDS comparator deglitch 2.5 4 5.75 µs
TOTW Thermal warning temperature TJ rising 130 150 170 °C
THYS Thermal warning hysteresis 20 °C
TOTSD Thermal shutdown temperature TJ rising 150 170 190 °C
THYS Thermal shutdown hysteresis 20 °C
tDS_DG 1µs (VDS_DG = 00b) should not be utilized for VDS_LVL 0.06, 0.08, and 0.10 V (VDS_LVL = 0000b, 0001b, 0010b)