SLVS855J July   2008  – March 2015 DRV8800 , DRV8801


  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  Logic Inputs
      2. 9.3.2  VREG (DRV8800 Only)
      3. 9.3.3  VPROPI (DRV8801 Only)
      4. 9.3.4  Charge Pump
      5. 9.3.5  Shutdown
      6. 9.3.6  Low-Power Mode
      7. 9.3.7  Braking
      8. 9.3.8  Diagnostic Output
      9. 9.3.9  Thermal Shutdown (TSD)
      10. 9.3.10 Overcurrent Protection
      11. 9.3.11 SENSE
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Operation
        1. Slow-Decay SR (Brake Mode)
        2. Fast Decay With Synchronous Rectification
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. Motor Voltage
        2. Power Dissipation
        3. Motor Current Trip Point
        4. Sense Resistor Selection
        5. Drive Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Bulk Capacitance
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The DRV880x devices are integrated motor driver solutions for brushed DC motors. The devices integrate a DMOS H-bridge, protection circuitry, and simple digital interface. The devices can be powered with a supply voltage between 8 and 36 V and are capable of providing an output current up to 2.8 A.

A PHASE-ENABLE interface allows for easy interfacing to the controller circuit. The PHASE input controls the direction of the H-bridge and the ENABLE input specifies whether the H-bridge is enabled or not.

Two MODE pins allow for specifying which current decay method the device utilizes. MODE1 specifies between fast decay or slow decay and MODE2 specifies between high side or low side slow decay.

The DRV8801 provides the option to monitor the motor winding current through a proportional voltage output.

9.2 Functional Block Diagrams

DRV8800 DRV8801 fbd_drv8800_slvs855.gifFigure 6. DRV8800 Functional Block Diagram
DRV8800 DRV8801 fbd_drv8801_slvs855.gifFigure 7. DRV8801 Functional Block Diagram

9.3 Feature Description

9.3.1 Logic Inputs

TI recommends using a high-value pullup resistor when logic inputs are pulled up to VDD. This resistor limits the current to the input in case an overvoltage event occurs. Logic inputs are nSLEEP, MODE, PHASE, and ENABLE. Voltages higher than 7 V on any logic input can cause damage to the input structure.

9.3.2 VREG (DRV8800 Only)

This output represents a measurement of the internal regulator voltage. This pin should be left disconnected. A voltage of approximately 7.5 V can be measured at this pin.

9.3.3 VPROPI (DRV8801 Only)

This output offers an analog voltage proportional to the winding current. Voltage at this terminal is five times greater than the motor winding current (VPROPI = 5×I). VPROPI is meaningful only if there is a resistor connected to the SENSE pin. If SENSE is connected to ground, VPROPI measures 0 V. During slow decay, VPROPI outputs 0 V. VPROPI can output a maximum of 2.5 V, since at 500 mV on SENSE, the H-bridge is disabled.

9.3.4 Charge Pump

The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF ceramic monolithic capacitor, CStorage, should be connected between VCP and VBB to act as a reservoir to run the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition, the outputs of the device are disabled.

9.3.5 Shutdown

As a measure to protect the device, faults caused by very high junction temperatures or low voltage on VCP disable the outputs of the device until the fault condition is removed. At power on, the UVLO circuit disables the drivers.

9.3.6 Low-Power Mode

Control input nSLEEP is used to minimize power consumption when the DRV880x is not in use. This disables much of the internal circuitry, including the internal voltage rails and charge pump. nSLEEP is asserted low. A logic high on this input pin results in normal operation. When switching from low to high, the user should allow a 1-ms delay before applying PWM signals. This time is needed for the charge pump to stabilize.

  • MODE 1 (MODE on the DRV8800)
  • Input MODE 1 is used to toggle between fast-decay mode and slow-decay mode. A logic high puts the device in slow-decay mode.

  • MODE 2 (DRV8801 only)
  • MODE 2 is used to select which set of drivers (high side versus low side) is used during the slow-decay recirculation. MODE 2 is meaningful only when MODE 1 is asserted high. A logic high on MODE 2 has current recirculation through the high-side drivers. A logic low has current recirculation through the low-side drivers.

9.3.7 Braking

The braking function is implemented by driving the device in slow-decay mode (MODE 1 pin is high) and deasserting the enable to low. Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worse-case braking situations – high-speed and high-inertia loads.

9.3.8 Diagnostic Output

The nFAULT pin signals a problem with the chip via an open-drain output. A motor fault, undervoltage condition, or TJ > 160°C drives the pin low. This output is not valid when nSLEEP puts the device into minimum power dissipation mode (that is, nSLEEP is low). nFAULT stays asserted (nFAULT = L) until VBB reaches VBBNFR to give the charge pump headroom to reach its undervoltage threshold. nFAULT is a status-only signal and does not affect any device functionality. The H-bridge portion still operates normally down to VBB = 8 V with nFAULT asserted.

9.3.9 Thermal Shutdown (TSD)

Two die-temperature monitors are integrated on the chip. As die temperature increases toward the maximum, a thermal warning signal is triggered at 160°C. This fault drives the nFAULT low, but does not disable the operation of the chip. If the die temperature increases further, to approximately 175°C, the full-bridge outputs are disabled until the internal temperature falls below a hysteresis of 15°C.

Table 1. Control Logic Table(1)

1 1 X X 1 H L Forward
0 1 X X 1 L H Reverse
X 0 1 0 1 L L Brake (slow decay)
X 0 1 1 1 H H Brake (slow decay)
1 0 0 X 1 L H Fast-decay synchronous rectification(2)
0 0 0 X 1 H L Fast-decay synchronous rectification(2)
X X X X 0 Z Z Sleep mode
(1) X = Don’t care, Z = high impedance
(2) To prevent reversal of current during fast-decay synchronous rectification, outputs go to the high-impedance state as the current approaches 0 A.

9.3.10 Overcurrent Protection

The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is not shorted to supply or ground. If a short is detected, the full-bridge outputs are turned off, flag nFAULT is driven low, and a 1.2-ms fault timer is started. After this 1.2-ms period, tOCP , the device is then allowed to follow the input commands and another turnon is attempted (nFAULT becomes high again during this attempt). If there is still a fault condition, the cycle repeats. If after tOCP expires it is determined the short condition is not present, normal operation resumes and nFAULT is deasserted.

9.3.11 SENSE

A low-value resistor can be placed between the SENSE pin and ground for current-sensing purposes. To minimize ground-trace IR drops in sensing the output current level, the current-sensing resistor should have an independent ground return to the star ground point. This trace should be as short as possible. For low-value sense resistors, the IR drops in the PCB can be significant, and should be taken into account.

Equation 1. DRV8800 DRV8801 equ2a_lvs855.gif


When selecting a value for the sense resistor, SENSE does not exceed the maximum voltage of ±500 mV. The H-bridge is disabled and enters recirculation when any current in the motor windings generates a SENSE voltage greater than or equal to 500 mV.

9.4 Device Functional Modes

9.4.1 Device Operation

The DRV880x supports a low power sleep mode through the nSLEEP pin. In this mode the device shuts down a majority of the internal circuitry including the internal voltage rails and charge pump. Bringing the nSLEEP pin HIGH will put the device back into its active state.

During normal operation the DRV880x is designed to operate a single brushed DC motor. The outputs are connected to each side on the motor coil, allowing for full bidirectional control. Slow-Decay SR (Brake Mode)

In slow-decay mode, both low-side sinking drivers turn on, allowing the current to circulate through the H-bridge’s low side (two sink drivers) and the load. Power dissipation I2R loses in the two sink DMOS drivers: Fast Decay With Synchronous Rectification

This decay mode is equivalent to a phase change where the opposite drivers are switched on. When in fast decay, the motor current is not allowed to go negative (direction change). Instead, as the current approaches zero, the drivers turn off. The power calculation is the same as the drive current calculation (see Equation 5).

DRV8800 DRV8801 curr_path1_lvs855.gifFigure 8. Current Path DRV8800
DRV8800 DRV8801 curr_path_lvs855.gifFigure 9. Current Path DRV8801