SLVSBA4F June   2012  – April 2021 DRV8837 , DRV8838


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 Dapper Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
      2. 7.3.2 Independent Half-Bridge Control
      3. 7.3.3 Sleep Mode
      4. 7.3.4 Power Supplies and Input Pins
      5. 7.3.5 Protection Circuits
        1. VCC Undervoltage Lockout
        2. Overcurrent Protection (OCP)
        3. Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
  8. Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Power Dissipation
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Related Links
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Independent Half-Bridge Control

Independent half-bridge control is possible with the DRV8837 without adopting more discrete components, as shown in Section 7.3.2. Two inductive loads (M1 and M2), which could be motors or solenoids, are tied between VM and OUTx, while the corresponding inputs (C1 and C2) are swapped before being fed to INx.

Figure 7-3 Independent Half-Bridge Control Circuit

The control logic for independent half-bridge drive is shown in Table 7-3. Columns INx and OUTx show the original logic of the DRV8837. Note that although a swap is included in this implementation, it is still valid that Cx = 1 spins a motor or energizes a solenoid connected at corresponding Mx, while Cx = 0, stops the motor or discharges the solenoid.

Table 7-3 Independent Half-Bridge Drive Logic
C1 C2 IN1 IN2 OUT1 OUT2 M1 M2
0 0 0 0 Z Z Off: Braking mode 1 Off: Braking mode 1
1 0 0 1 L H On: Driving mode Off: Braking mode 2
0 1 1 0 H L Off: Braking mode 2 On: Driving mode
1 1 1 1 L L On: Driving mode On: Driving mode

Figure 7-4 shows the driving mode and the two current decay paths during current regulation when PWM input control is used. The driving mode occurs when the corresponding half-bridge Cx signal is HIGH. When the Cx signal is LOW, the corresponging half bridge can go into either braking mode 1 or braking mode 2. In braking mode 1, both the high- and low-side MOSFETs of the half-bridge are tri-stated, and the recirculation current flows through the body diode of the high-side MOSFET as well as the motor itself. This braking mode happens when both C1 and C2 are LOW. If one of the Cx input is LOW and the other HIGH, the half-bridge corresponding to the LOW Cx input will go into braking mode 2. In braking mode 2, the low-side FET is OFF while its high-side counterpart is ON. The recirculation current flows through the high-side MOSFET and the motor.

GUID-20210323-CA0I-BJCF-G1HT-V3CGMN1VSXGT-low.png Figure 7-4 Normal Driving and Current Decay Modes

When each of the Cx inputs are independently controlled with different PWM frequencies and duty cycle, each half-bridge will go into a combination of braking mode 1 and braking mode 2. Figure 7-5 show a driving and decay example with independent PWM inputs. If the half-bridge spends more time in braking mode 1, the motor average speed will be lower since more power is dissipated through the MOSFET body diode. To reduce the power dissipated during braking mode 1, it is recommended to placed Schottky diodes with forward voltage less than 0.6V across the motors as shown in Figure 7-6. Note that if On/Off control mode (constant HIGH or LOW at inputs) is used, the two braking modes do not interact with each other and hence have no effect on the average speed of the two motors.

GUID-20210323-CA0I-GHXX-KRTJ-DDN0RT4ST9HM-low.png Figure 7-5 Driving and Decay Examples with Independent PWM Inputs
GUID-20210323-CA0I-QVKH-JBDR-1V0ZPNSP6QFL-low.png Figure 7-6 Improved Application Circuit for Better Motor Performance