SLVSI22 August   2025 DRV8844A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Stage
      2. 6.3.2 Logic Inputs
      3. 6.3.3 Bridge Control
      4. 6.3.4 Charge Pump
      5. 6.3.5 Protection Circuits
        1. 6.3.5.1 Overcurrent Protection (OCP)
        2. 6.3.5.2 Thermal Shutdown (TSD)
        3. 6.3.5.3 Undervoltage Lockout (UVLO)
      6. 6.3.6 CLR_FAULT and nSLEEP Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Application Information
      1. 7.2.1 Driving Solenoid Loads
      2. 7.2.2 Driving Stepper Motor
      3. 7.2.3 Driving Brushed DC motor
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Considerations
        1. 7.4.3.1 Heatsinking
      4. 7.4.4 Power Dissipation
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Community Resources
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

DRV8844A DGQ Package28-Pin HVSSOPTop View Figure 4-1 DGQ Package28-Pin HVSSOPTop View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS
NAME NO.
POWER AND GROUND
CP1 1 P Charge pump flying capacitor Connect a 0.01μF 100V capacitor between CP1 and CP2.
CP2 2 P Charge pump flying capacitor
LGND 19 P Logic input reference ground Connect to logic ground. This can be any voltage between VNEG and VM – 8V.
V3P3OUT 15 P 3.3V regulator output Bypass to VNEG with a 0.47μF 6.3V ceramic capacitor. Can be used to supply VREF.
VCP 3 P High-side gate drive voltage Connect a 0.1μF 16V ceramic capacitor to VM.
VM 4, 13 P Main power supply Connect to motor supply (8V to 60V). Both pins must be connected to same supply. Bypass to VNEG with a 10µF (minimum) capacitor.
SRC1 6 P Low-side FET source for OUT1 Connect to VNEG directly or through optional current-sense resistor
SRC2

7

 P Low-side FET source for OUT2
SRC3 10 P Low-side FET source for OUT3
SRC4 11 P Low-side FET source for OUT4
VNEG 28, PPAD P Negative power supply (dual supplies) or ground (single supply)
CONTROL
EN1 26 I Channel 1 enable Logic high enables OUT1. Internal pulldown.
EN2 24 I Channel 2 enable Logic high enables OUT2. Internal pulldown.
EN3 22 I Channel 3 enable Logic high enables OUT3. Internal pulldown.
EN4 20 I Channel 4 enable Logic high enables OUT4. Internal pulldown.
IN1 27 I Channel 1 input Logic input controls state of OUT1. Internal pulldown.
IN2 25 I Channel 2 input Logic input controls state of OUT2. Internal pulldown.
IN3 23 I Channel 3 input Logic input controls state of OUT3. Internal pulldown.
IN4 21 I Channel 4 input Logic input controls state of OUT4. Internal pulldown.
CLR_FAULT 16 I Clear Fault input Negative Edge clears latched faults in affected channels
nSLEEP 17 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown.
STATUS
nFAULT 18 OD Fault Logic low when in fault condition (overtemperature, overcurrent, UVLO). Open-drain output.
OUTPUT
OUT1 5 O Output 1 Connect to loads
OUT2 8 O Output 2
OUT3 9 O Output 3
OUT4 12 O Output 4
NO CONNECT
NC 14 — No connect No connection to these pins
(1) I = input, O = output, OD = open-drain output, P = power