SLVSEC9C Data sheet

SLVSEC9C September 2019 – February 2020 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1

PRODUCTION DATA.

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Mechanical Data (Package|Pins)

PWP|24
- MPDS372A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7.5 Electrical Characteristics

at T_J = –40°C to +150°C, V_VM = 4.5 to 32 V (Main Supply), V_VDD= 3 to 5.5 V (Logic Supply) (unless otherwise noted). Typical limits apply for T_A = 25°C, V_VM = 13.5 V, V_VDD = 3.3 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES (VDD, VM)
I_VMQ	VM sleep mode current	V_VM= 13.5 V, nSLEEP = 0, T_A = 25 °C		0.35	1	µA
I_VMQ	VM sleep mode current	V_VM = 13.5 V, nSLEEP = 0, T_A = 125 °C			2	µA
I_VDDQ	VDD sleep mode current	V_VM = 13.5 V, V_VDD = 3.3 V, nSLEEP = 0, T_A = 25 °C		0.01	0.3	µA
I_VDDQ	VDD sleep mode current	V_VM= 13.5 V, V_VDD = 3.3 V, nSLEEP = 0, T_A = 125 °C			2	µA
I_VMS	VM standby mode current	V_VM= 13.5 V, nSLEEP = 1, Driver = 'OFF', T_A = 25 °C		0.2	0.5	mA
I_VMS	VM standby mode current	V_VM= 13.5 V, nSLEEP = 1, Driver = 'OFF', T_A = 125 °C			0.5	mA
I_VDDS	VDD standby mode current	V_VM= 13.5 V, V_VDD = 3.3 V, nSLEEP = 1, SPI = 'OFF', T_A= 25 °C		0.6	1	mA
I_VDDS	VDD standby mode current	V_VM= 13.5 V, V_VDD = 3.3 V, nSLEEP = 1, SPI = 'OFF', T_A = 125 °C			1	mA
I_VM	VM operating mode current	V_VM= 13.5 V, nSLEEP = 1, All High-Side FETs = 'ON', T_A = 25 °C		2.6	5	mA
I_VM	VM operating mode current	V_VM = 13.5 V, nSLEEP = 1, All High-Side FETs = 'ON', T_A = 125 °C			5	mA
I_VDD	VDD operating mode current	V_VM = 13.5 V, V_VDD = 3.3 V, nSLEEP = 1, All High-Side FETs = 'ON', SPI = 'ON' (5 MHz), T_A = 25 °C		2.8	5	mA
I_VDD	VDD operating mode current	V_VM = 13.5 V, V_VDD = 3.3 V, nSLEEP = 1, All High-Side FETs = 'ON', SPI = 'ON' (5 MHz), T_A = 125 °C			5	mA
t_WAKE	Wake-up time	nSLEEP high to SPI ready			200	µs
t_SLEEP	Turnoff time	nSLEEP low to device sleep			20	µs
LOGIC-LEVEL INPUTS (nSLEEP, SCLK, SDI)
V_IL	Input logic low voltage		0		0.3*VDD	V
V_IH	Input logic high voltage		0.7*VDD		VDD	V
V_HYS	Input logic hysteresis		200			mV
I_IL	Input logic low current	V_IN = 0 V	–1		1	µA
I_IH	Input logic high current	V_IN = V_VDD		34	75	µA
C_ID	Input capacitance				15	pF
LOGIC-LEVEL INPUTS (nSCS)
V_IL	Input logic low voltage		0		0.3*VDD	V
V_IH	Input logic high voltage		0.7*VDD		VDD	V
V_HYS	Input logic hysteresis		200			mV
I_IL	Input logic low current	V_IN = 0 V		34	75	µA
I_IH	Input logic high current	V_IN = V_VDD	–1		1	µA
C_ID	Input capacitance				15	pF
OPEN-DRAIN OUTPUTS (nFAULT)
V_OL	Output logic low voltage	I_OD = 5 mA	0		0.4	V
I_OH	Output logic high current	V_OD = 5 V	–1		1	µA
C_OD	Output capacitance				15	pF
PUSH-PULL OUTPUTS (SDO)
V_OL	Output logic low voltage	I_OP = 5 mA	0		0.4	V
V_OH	Output logic high voltage	I_OP = 5 mA	VDD–0.6		VDD	V
I_OL	Output logic low current	V_OP = 0 V	–1		1	µA
I_OH	Output logic high current	V_OP = V_VDD	–1		1	µA
C_OD	Output capacitance				30	pF
DRIVER OUTPUTS (OUTx)
R_DS(ON)	High-side MOSFET on resistance	V_VM= 13.5 V, I_OUT = 0.5 A, T_A = 25°C		0.75	1.1	Ω
	High-side MOSFET on resistance	V_VM= 13.5 V, I_OUT = 0.5 A, T_A = 125°C			1.5	Ω
	Low-side MOSFET on resistance	V_VM= 13.5 V, I_OUT = 0.5 A, T_A = 25°C		0.75	1.1	Ω
	Low-side MOSFET on resistance	V_VM= 13.5 V, I_OUT = 0.5 A, T_A = 125°C			1.5	Ω
SR	Output rise and fall time (high-side and low-side)	V_VM = 13.5 V, 10-90%, R_LOAD = 27 Ω, HBx_SR = 0b		0.6		V/µs
SR	Output rise and fall time (high-side and low-side)	V_VM = 13.5 V, 10-90%, R_LOAD = 27 Ω, HBx_SR = 1b		2.5		V/µs
t_DEAD	Output dead time (high to low / low to high)	V_VM= 13.5 V, SR = 0, HS/LS driver OFF to LS/HS driver ON	8	20	32	µs
t_DEAD	Output dead time (high to low / low to high)	V_VM= 13.5 V, SR = 1, HS/LS driver OFF to LS/HS driver ON	2	5	15	µs
t_PD	Propagation delay (high-side / low-side ON/OFF)	High-side ON or low-side ON command (SPI last transition) to OUTx transition from Hi-Z state, SR = 0	5	12	25	µs
t_PD	Propagation delay (high-side / low-side ON/OFF)	High-side ON or low-side ON command (SPI last transition) to OUTx transition from Hi-Z state, SR = 1	3	5	10	µs
I_LEAK	Leakage current low-side	V_OUTx= 13.5 V, nSLEEP = 1, SR = 0b		6	10	µA
		V_OUTx= 13.5 V, nSLEEP = 1, SR = 1b		20	35	µA
		V_OUTx= 13.5 V, nSLEEP = 0		4	15	µA
	Leakage current high-side	V_OUTx= 0 V, nSLEEP = 1			2	µA
	Leakage current high-side	V_OUTx= 0 V, nSLEEP = 0			2	µA
PWM MODE
f_PWM	PWM switching frequency	PWM_CHx_FREQ = 00b	56	80	104	Hz
		PWM_CHx_FREQ = 01b	70	100	130	Hz
		PWM_CHx_FREQ = 10b	140	200	260	Hz
		PWM_CHx_FREQ = 11b	1400	2000	2600	Hz
PROTECTION CIRCUITS
V_UVLO	Supply undervoltage lockout (UVLO)	Supply rising	4.0		4.5	V
V_UVLO	Supply undervoltage lockout (UVLO)	Supply falling	3.8		4.3	V
V_{UVLO_HYS}	Supply undervoltage lockout hysteresis	Rising to falling theshold		200		mV
t_UVLO	Supply undervoltage deglitch time			10		µs
V_OVP	Supply overvoltage protection (OVP)	Supply rising, EXT_OVP = 0b	21		25	V
		Supply falling, EXT_OVP = 0b	20		24	V
		Supply rising, EXT_OVP = 1b	32.7		35	V
		Supply falling, EXT_OVP = 1b	32		34.3	V
V_{OVP_HYS}	Supply overvoltage protection hysteresis	Rising to falling theshold, EXT_OVP = 0b		1		V
V_{OVP_HYS}	Supply overvoltage protection hysteresis	Rising to falling theshold, EXT_OVP = 1b		0.7		V
t_OVP	Supply overvoltage deglitch time			10		µs
V_POR	Logic undervoltage (POR)	Supply rising	2.45		3	V
V_POR	Logic undervoltage (POR)	Supply falling	2.4		2.95	V
V_{POR_HYS}	Logic undervoltage hysteresis	Rising to falling theshold		75		mV
I_OCP	Overcurrent protection trip point⁽¹⁾⁽²⁾		1.3	1.8	2.3	A
t_OCP	Overcurrent protection deglitch time	OCP_DEG = 000b	6	10	14	µs
		OCP_DEG = 001b	2.6	5	7.9	µs
		OCP_DEG = 010b	0.4	2.5	5.9	µs
		OCP_DEG = 011b	0.1	1	3.4	µs
		OCP_DEG = 100b	38.2	60	76.6	µs
		OCP_DEG = 101b	23.1	40	51.9	µs
		OCP_DEG = 110b	18.5	30	41.5	µs
		OCP_DEG = 111b	8.4	20	31.6	µs
I_OLD	Open load detection current	Current flowing from VM to OUTx (High-Side = ON) or OUTx to GND (Low-Side = ON)	2	9	18	mA
I_{OLD_NEG}	Negative open load detection current	Current flowing from OUTx to VM (High-Side = ON) or GND to OUTx (Low-Side = ON)	2	15	30	mA
I_{OLD_LOW}	Open load detection current in low current OLD mode	Current flowing from VM to OUTx (High-Side = ON) or OUTx to GND (Low-Side = ON)	0.2	0.8	2	mA
I_{OL_GND}	Passive OLD current	DRV8908/6/4, FETs in Hi-Z state, current from OUTx to GND during OLD trip		113		µA
V_{OL_GND}	Passive OLD voltage threshold	DRV8908/6/4, FETs in Hi-Z state, voltage at OUTx during OLD trip for GND-connected load		3.3		V
I_{OL_VM}	Passive OLD current	DRV8908/6/4, FETs in Hi-Z state, current from VM to OUTx for OLD trip, HBX_VM_POLD = 0b		118		µA
V_{OL_VM}	Passive OLD voltage threshold	DRV8908/6/4, FETs in Hi-Z state, voltage at OUTx during OLD trip for VM-connected load, HBX_VM_POLD = 0b		1.2		V
I_{OL_VM}	Passive OLD current	DRV8908/6/4, FETs in Hi-Z state, current from VM to OUTx for OLD trip, HBX_VM_POLD = 1b		547		µA
V_{OL_VM}	Passive OLD voltage threshold	DRV8908/6/4, FETs in Hi-Z state, voltage at OUTx during OLD trip for VM connceted load, HBX_VM_POLD = 1b		1.8		V
R_OL	Passive OLD detect resistance threshold	DRV8908/6/4, FETs in Hi-Z state, Full bridge connection	5		100	kΩ
R_OL	Passive OLD detect resistance threshold	DRV8908/6/4, FETs in Hi-Z State, Load connected to GND	5		100	kΩ
R_OL	Passive OLD detect resistance threshold	DRV8908/6/4, FETs in Hi-Z State, Load connected to VM, HBX_VM_POLD = 0b	5		400	kΩ
R_OL	Passive OLD detect resistance threshold	DRV8908/6/4, FETs in Hi-Z State, Load connected to VM, HBX_VM_POLD = 1b	5		100	kΩ
t_OLD	Open load deglitch time	Active OLD (Continuous Mode)	2	3	4	ms
t_OLD	Open load deglitch time	Active OLD (PWM Mode)	150	200	300	µs
T_OTW	Thermal warning temperature	Die temperature (T_j)	120	140	170	°C
T_{OTW_HYS}	Thermal warning hysteresis	Die temperature (T_j)		20		°C
T_OTSD	Thermal shutdown temperature	Die temperature (T_j)	150	175	200	°C
T_{OTSD_HYS}	Thermal shutdown hysteresis	Die temperature (T_j)		20		°C

(1) For 20-V < V_VM < 28-V, the OCP deglicth time must be limited to 10-µs (Default Deglitch Value, OCP_DEG = 000b).

(2) For V_VM> 28 V, the OCP deglicth time must be limited to 1-µs (Lowest Deglitch Value, OCP_DEG = 011b).