SLOSE62A January   2021  – May 2022 DRV8935

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control and Current Regulation
      2. 7.3.2 Decay Modes
        1. 7.3.2.1 Blanking time
      3. 7.3.3 Charge Pump
      4. 7.3.4 Linear Voltage Regulators
      5. 7.3.5 Logic and Quad-Level Pin Diagrams
      6. 7.3.6 nFAULT Pin
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.7.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.7.3 Overcurrent Protection (OCP)
        4. 7.3.7.4 Thermal Shutdown (OTSD)
        5. 7.3.7.5 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 nSLEEP Reset Pulse
      4. 7.4.4 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
      3. 8.2.3 Power Dissipation Calculation and Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.1 Current Regulation

When an output load is connected to the VM supply, the load current can be regulated to the ITRIP level. The ITRIP current level for OUT1 and OUT2 outputs is controlled by the VREF12 pin, and the ITRIP level for OUT3 and OUT4 outputs is controlled by the VREF34 pin. The ITRIP current (ITRIP) can be calculated as ITRIP (A) = VREF (V) / 1.32 (V/A). The VREF voltage can be programmed by connecting resistor dividers from DVDD pin to ground. Both VREF pins can be tied together to program the same ITRIP current for all four output channels.