SNLS658 December 2020 DS160PR810
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Receiver | ||||||
RL_{RX-DIFF} | Input differential return loss | 50 MHz to 1.25 GHz | -25 | dB | ||
1.25 GHz to 2.5 GHz | -22 | dB | ||||
2.5 GHz to 4.0 GHz | -21 | dB | ||||
4.0 GHz to 8.0 GHz | -16 | dB | ||||
XT_{RX} | Receive-side pair-to-pair isolation | Pair-to-pair isolation (SDD21) between two adjacent receiver pairs from 10 MHz to 8 GHz. | -47 | dB | ||
Transmitter | ||||||
V_{TX-AC-CM-PP} | Tx AC peak-to-peak common mode voltage | Measured with lowest EQ, VOD = L2; PRBS-7, 16 Gbps, over at least 10E6 bits using a bandpas filter from 30 Khz to 500 Mhz | 50 | mVpp | ||
V_{TX-CM-DC-ACTIVE-IDLE-DELTA} | Absolute delta of DC common mode voltage during L0 and Electrical Idle | V_{TX-CM-DC} = |V_{OUTn+} + V_{OUTn–}|/2, measured by taking the absolute difference of V_{TX-CM-DC} during PCIe state L0 and Electrical Idle | 0 | 100 | mV | |
V_{TX-CM-DC-LINE-DELTA} | Absolute delta of DC common mode voltage between V_{OUTn+} and V_{OUTn–} during L0 | Measured by taking the absolute difference of V_{OUTn+} and V_{OUTn– }during PCIe state L0 | 10 | mV | ||
V_{TX-IDLE-DIFF-AC-p} | AC Electrical Idle differential output voltage | Measured by taking the absolute difference of V_{OUTn+} and V_{OUTn– }during Electrical Idle, measured with a band-pass filter consisting of two first-order filters. The high-pass and low-pass -3-dB bandwidths are 10 kHz and 1.25 GHz, respectively - zero at input | 0 | 10 | mV | |
V_{TX-IDLE-DIFF-DC} | DC Electrical Idle differential output voltage | Measured by taking the absolute difference of V_{OUTn+} and V_{OUTn– }during Electrical Idle, measured with a first-order low-pass Filter with –3-dB bandwidth of 10 kHz | 0 | 5 | mV | |
V_{TX-RCV-DETECT} | Amount of voltage change allowed during receiver detection | Measured while Tx is sensing whether a low-impedance Receiver is present. No load is connected to the driver output | 0 | 600 | mV | |
RL_{TX-DIFF} | Output differential return loss | 50 MHz to 1.25 GHz | -20 | dB | ||
1.25 GHz to 2.5 GHz | -18 | dB | ||||
2.5 GHz to 4.0 GHz | -18 | dB | ||||
4.0 GHz to 8.0 GHz | -17 | dB | ||||
XT_{TX} | Transmit-side pair-to-pair isolation | Minimum pair-to-pair isolation (SDD21) between two adjacent transmitter pairs from 10 MHz to 8 GHz. | -48 | dB | ||
Device Datapath | ||||||
T_{PLHD/PHLD} | Input-to-output latency (propagation delay) through a data channel | For either low-to-high or high-to-low transition. | 90 | 120 | ps | |
L_{TX-SKEW} | Lane-to-lane output skew | Between any two lanes within a single transmitter. | -20 | 20 | ps | |
T_{RJ-DATA} | Additive random jitter with data | Jitter through redriver minus the calibration trace. 16Gbps PRBS15. Minimal input/output channels. Minimum EQ. 800 mVpp-diff input swing. | 70 | fs | ||
T_{RJ-INTRINSIC} | Intrinsic additive random jitter with clock | Jitter through redriver minus the calibration trace. 8 Ghz CK. Minimal input/output channels. Minimum EQ. 400 mVpp-diff input swing. | 90 | fs | ||
JITTER_{TOTAL-DATA} | Additive total jitter with data | Jitter through redriver minus the calibration trace. 16 Gbps PRBS15. Minimal input/output channels. Minimum EQ. 800 mVpp-diff input swing. | 4 | ps | ||
JITTER_{TOTAL-INTRINSIC} | Intrinsic additive total jitter with clock | Jitter through redriver minus the calibration trace. 8 Ghz CK. Minimal input/output channels. Minimum EQ. 800 mVpp-diff input swing. | 1 | ps | ||
FLAT-GAIN | Flat gain (DC and AC) input to output | Minimum EQ, GAIN1/0=L0 | -4.2 | dB | ||
Minimum EQ, GAIN1/0=L1 | -1.8 | dB | ||||
Minimum EQ, GAIN1/0=L2 | 0.25 | dB | ||||
Minimum EQ, GAIN1/0=L3 (float, default) | 2 | dB | ||||
EQ-MAX_{8G} | EQ boost at max setting (EQ INDEX = 15) | AC gain at 8 GHz relative to gain at 100 MHz. GAIN1/0=L3 (float, default). | 18.0 | dB | ||
DCGAIN_{VAR} | DC gain variation | GAIN1/0 = L2, minimum EQ setting. Max-Min. | -2.3 | 1.7 | dB | |
EQGAIN_{VAR} | EQ boost variation | At 8 Ghz. GAIN1/0 = L2, maximum EQ setting. Max-Min. | -3.3 | 3.7 | dB | |
LIN_{DC} | Output DC linearity | GAIN1/0 = L3 (float, default). 128T pattern at 2.5 Gbps. | 1000 | mVpp | ||
LIN_{AC} | Output AC linearity | GAIN1/0 = L3 (float, default). 1T pattern at 16 Gbps. | 750 | mVpp |