SNLS542C October   2016  – December 2020 DS280MB810

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements – Serial Management Bus Interface
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Data Path Operation
      2. 8.3.2 AC-coupled Receiver Inputs
      3. 8.3.3 Signal Detect
      4. 8.3.4 2-Stage CTLE
      5. 8.3.5 Driver DC Gain Control
      6. 8.3.6 2x2 Cross-point Switch
      7. 8.3.7 Configurable SMBus Address
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Slave Mode Configuration
      2. 8.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 8.5 Programming
      1. 8.5.1 Transfer of Data with the SMBus Interface
    6. 8.6 Register Maps
      1. 8.6.1 Register Types: Global, Shared, and Channel
      2. 8.6.2 Global Registers: Channel Selection and ID Information
      3. 8.6.3 Shared Registers
      4. 8.6.4 Channel Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Reach Extension
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Front-Port Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Pattern Generator Characteristics
        2. 9.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 9.2.3.3 Equalizing High Pre-Channel Loss
        4. 9.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
    3. 9.3 Initialization Set Up
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 Stripline Example
      2. 11.2.2 Microstrip Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.3 Shared Registers

Table 8-3 Shared Register Map
Addr [HEX]BitDefault [HEX]ModeEEPROMFieldDescription
0x000x01General
70RNI2C_ADDR[3]I2C strap observation. The device 7-bit slave address is 0x18 + I2C_ADDR[3:0].
60RNI2C_ADDR[2]
50RNI2C_ADDR[1]
40RNI2C_ADDR[0]
30RNRESERVEDRESERVED
20RNRESERVEDRESERVED
10RNRESERVED1'b when Quad1 Shared registers enabled.
01RNRESERVED1'b when Quad0 Shared registers enabled.
0x010x02Version Revision
70RNRESERVEDRESERVED
60RNRESERVEDRESERVED
50RNRESERVEDRESERVED
40RNRESERVEDRESERVED
30RNRESERVEDRESERVED
20RNRESERVEDRESERVED
11RNRESERVEDRESERVED
00RNRESERVEDRESERVED
0x020x00Channel Control
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x030x00Channel Control
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x040x01General
70RWNRESERVEDRESERVED
60RWSCNRST_I2C_REGS1: Reset shared registers, bit is self-clearing.
0: Normal operation
50RWSCNRST_I2C_MAS1: Self-clearing reset for I2C master.
0: Normal operation
40RWNFRC_EEPRM_RD1: Override EN_SMB and input chain status to force EEPROM Configuration.
0: Normal operation
30RWNRESERVEDRESERVED
20RWNREGS_CLOCK_ENRESERVED
10RWNI2C_MAS_CLK_ENRESERVED
01RWNI2CSLV_CLK_ENRESERVED
0x050x00General
70RWNDISAB_EEPRM_CFG1: Disable Master Mode EEPROM Configuration (If not started, not effective midway or after configuration).
0: Normal operation
60RWNCRC_ENRESERVED
50RWNML_TEST
_CONTROL		RESERVED
40RNEEPROM_READING
_DONE		Sets 1 when EEPROM reading is done.
30RNRESERVEDRESERVED
20RYCAL_CLK_INV_DIS1: Disable the inversion of CAL_CLK_OUT.
0: Normal operation, CAL_CLK_OUT is inverted with respect to CAL_CLK_IN.
10RNMUX_CONFIG_PIN_CTRL1: MUXSEL0_TEST0 and MUXSEL1_TEST1 are used to configure the cross-point mux. MUXSEL0_TEST0 controls the cross-point for channels 0–1 and 4–5. MUXSEL1_TEST1 controls the cross-point for channels 2–3 and 6–7. For mux pin-control, Reg_05[0] must also be 0, which is the power-on default value.
0: Cross-point mux is configured on a per-channel basis with Reg_0x06[0].
00RNTEST0_AS_CAL
_CLK		RESERVED
0x060x00General
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x070x00General
70RWNRESERVEDRESERVED
60RNCAL_CLK_DET1: Indicates that CAL_CLK has been detected.
0: Indicates that CAL_CLK has not been detected.
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWNMR_CAL_CLK_DET
_DIS		1: Disable CAL_CLK detect.
0: Enable CAL_CLK detect.
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWYDIS_CAL_CLK_OUT1: Disable CAL_CLK_OUT, output is high-Z.
0: Enable CAL_CLK_OUT.
0x080x00General
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x090x00General
70RNRESERVEDRESERVED
60RNRESERVEDRESERVED
50RNRESERVEDRESERVED
40RNRESERVEDRESERVED
30RNRESERVEDRESERVED
20RNRESERVEDRESERVED
10RNRESERVEDRESERVED
00RNRESERVEDRESERVED
0x0A0x00General
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RNRESERVEDRESERVED
00RNRESERVEDRESERVED
0x0B0x00
70RNEECFG_CMPLT11: Not valid.
10: EEPROM load completed successfully.
60RNEECFG_FAIL01: EEPROM load failed after 64 attempts.
00: EEPROM load in progress.
50RNEECFG_ATMPT[5]Indicates number of attempts made to load EEPROM image.
40RNEECFG_ATMPT[4]
30RNEECFG_ATMPT[3]
20RNEECFG_ATMPT[2]
10RNEECFG_ATMPT[1]
00RNEECFG_ATMPT[0]
0x0C0x91
71RWNI2C_FAST1: EEPROM load uses Fast I2C Mode (400 kHz).
0: EEPROM load uses Standard I2C Mode (100 kHz).
60RWNI2C_SDA_HOLD[2]Internal SDA Hold Time
This field configures the amount of internal hold time provided for the SDA input relative to the SDC input. Units are 100 ns.
50RWNI2C_ SDA_HOLD[1]
41RWNI2C_ SDA_HOLD[0]
30RWNI2C_FLTR_DEPTH[3]I2C Glitch Filter Depth
This field configures the maximum width of glitch pulses on the SDC and SDA inputs that will be rejected. Units are 100 ns.
20RWNI2C_FLTR_DEPTH[2]
10RWNI2C_FLTR_DEPTH[1]
01RWNI2C_FLTR_DEPTH[0]