SNLS542C October   2016  – December 2020 DS280MB810

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements – Serial Management Bus Interface
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Data Path Operation
      2. 8.3.2 AC-coupled Receiver Inputs
      3. 8.3.3 Signal Detect
      4. 8.3.4 2-Stage CTLE
      5. 8.3.5 Driver DC Gain Control
      6. 8.3.6 2x2 Cross-point Switch
      7. 8.3.7 Configurable SMBus Address
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Slave Mode Configuration
      2. 8.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 8.5 Programming
      1. 8.5.1 Transfer of Data with the SMBus Interface
    6. 8.6 Register Maps
      1. 8.6.1 Register Types: Global, Shared, and Channel
      2. 8.6.2 Global Registers: Channel Selection and ID Information
      3. 8.6.3 Shared Registers
      4. 8.6.4 Channel Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Reach Extension
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Front-Port Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Pattern Generator Characteristics
        2. 9.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 9.2.3.3 Equalizing High Pre-Channel Loss
        4. 9.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
    3. 9.3 Initialization Set Up
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 Stripline Example
      2. 11.2.2 Microstrip Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER
WchannelPower consumption per active channelChannel enabled with maximum driver VOD (DRV_SEL_VOD = 3).
Static power consumption not included.		82109 (1)mW
Channel enabled with minimum driver VOD (DRV_SEL_VOD = 0).
Static power consumption not included.		75100 (1)mW
Wchannel_CPPower consumption per active channel, cross-point enabledChannel enabled, cross-point enabled, and maximum driver VOD (DRV_SEL_VOD = 3).
Static power consumption not included.		82109 (1)mW
Channel enabled, cross-point enabled, and minimum driver VOD (DRV_SEL_VOD = 0).
Static power consumption not included.		75100 (1)mW
Wchannel_FOPower consumption per active channel, fanout enabledChannel enabled, fanout enabled, and maximum driver VOD (DRV_SEL_VOD = 3).
Static power consumption not included.		6995 (1)mW
Channel enabled, fanout enabled, and minimum driver VOD (DRV_SEL_VOD = 0).
Static power consumption not included.		6186 (1)mW
Wstatic_totalIdle (static) mode total device power consumptionChannels disabled and powered down
(DRV_PD = 1, EQ_PD = 1).		110173 (1)mW
ItotalActive mode total device supply current consumptionAll channels enabled with maximum driver VOD
(DRV_SEL_VOD = 3).		307389mA
All channels enabled with minimum driver VOD
(DRV_SEL_VOD = 0).		283361mA
Itotal_CPActive mode total device supply current consumption, cross-point enabledAll channels enabled, cross-point enabled, and maximum driver VOD
(DRV_SEL_VOD = 3).		307389mA
All channels enabled, cross-point enabled, and minimum driver VOD
(DRV_SEL_VOD = 0).		283361mA
Itotal_FOActive mode total device supply current consumption, fanout enabledAll channels enabled, fanout enabled, and maximum driver VOD
(DRV_SEL_VOD = 3).		264346mA
All channels enabled, fanout enabled, and minimum driver VOD
(DRV_SEL_VOD = 0).		240318mA
Istatic_totalIdle (static) mode total device supply current consumptionAll channels disabled and powered down
(DRV_PD = 1, EQ_PD = 1).		4466mA
LVCMOS DC SPECIFICATIONS (CAL_CLK_IN, CAL_CLK_OUT, READ_EN_N, ALL_DONE_N, MUXSEL[1:0])
VIHHigh level input voltage1.75VDDV
READ_EN_N pin only1.753.6V
VILLow level input voltageGND0.7V
VOHHigh level output voltageIOH = 4 mA2V
VOLLow level output voltageIOL = -4 mA0.4V
IIHInput high leakage currentVinput = VDD, MUXSEL[1:0] pins16µA
Vinput = VDD, CAL_CLK_IN pin66µA
Vinput = VDD, READ_EN_N pin (2)1µA
IILInput low leakage currentVinput = 0 V, MUXSEL[1:0] pins-38µA
Vinput = 0 V, CAL_CLK_IN pin (3)-1µA
Vinput = 0 V, READ_EN_N pin (2)-55µA
4-LEVEL LOGIC ELECTRICAL SPECIFICATIONS (APPLIES TO 4-LEVEL INPUT CONTROL PINS ADDR0, ADDR1, and EN_SMB)
IIHInput high leakage current105µA
IILInput low leakage current-253µA
VTHHigh level (1) input voltage0.95 * VDDV
Float level input voltage0.67 * VDDV
10 K to GND input voltage0.33 * VDDV
Low level (0) input voltage0.1V
HIGH-SPEED DIFFERENTIAL INPUTS (RXnP, RXnN)
BSTCTLE high-frequency boostMeasured with maximum CTLE setting and maximum BW setting (EQ_BST1 = 7, EQ_BST2 = 7, EQ_BW = 3). Boost is defined as the gain at 14 GHz relative to 20 MHz.25.6dB
Measured with maximum CTLE setting and maximum BW setting (EQ_BST1 = 7, EQ_BST2 = 7, EQ_BW = 3). Boost is defined as the gain at 12.9 GHz relative to 20 MHz.25.3dB
BSTCTLE high-frequency boostMeasured with minimum CTLE setting and minimum BW setting (EQ_BST1 = 0, EQ_BST2 = 0, EQ_BW = 0, EQ_EN_BYPASS = 1). Boost is defined as the gain at 14 GHz relative to 20 MHz.2.4dB
Measured with minimum CTLE setting and minimum BW setting (EQ_BST1 = 0, EQ_BST2 = 0, EQ_BW = 0, EQ_EN_BYPASS = 1). Boost is defined as the gain at 12.9 GHz relative to 20 MHz.2.4dB
BSTdeltaCTLE high-frequency gain variationMeasured with maximum CTLE setting (EQ_BST1 = 7, EQ_BST2 = 7). Gain variation is defined as the total change in gain at 14 GHz due to temperature and voltage variation.< 3dB
Measured with maximum CTLE setting (EQ_BST1 = 7, EQ_BST2 = 7). Gain variation is defined as the total change in gain at 12.9 GHz due to temperature and voltage variation.< 3dB
BSTdeltaCTLE high-frequency gain variationMeasured with minimum CTLE setting (EQ_BST1 = 0, EQ_BST2 = 0, EQ_EN_BYPASS = 1). Gain variation is defined as the total change in gain at 14 GHz due to temperature and voltage variation.< 2dB
Measured with minimum CTLE setting (EQ_BST1 = 0, EQ_BST2 = 0, EQ_EN_BYPASS = 1). Gain variation is defined as the total change in gain at 12.9 GHz due to temperature and voltage variation.< 2dB
RLSDD11Input differential return loss50 MHz to 3.7 GHz< -14dB
3.7 GHz to 10 GHz< -12dB
10 GHz to 14.1 GHz< -8dB
14.1 GHz to 20 GHz< -6dB
RLSDC11Input differential-to-common-mode return loss100 MHz to 3.3 GHz< -35dB
3.3 GHz to 12.9 GHz< -26dB
12.9 GHz to 20 GHz< -22dB
RLSCC11Input common-mode return loss100 MHz to 10 GHz< -7dB
10 GHz to 20 GHz< -8dB
VSDATAC signal detect assert (ON) differential voltage threshold levelMinimum input peak-to-peak amplitude level at device pins required to assert signal detect. 25.78125 Gbps with PRBS7 pattern and 20 dB loss channel.196mVpp
VSDDTAC signal detect de-assert (OFF) differential voltage threshold levelMaximum input peak-to-peak amplitude level at device pins which causes signal detect to de-assert. 25.78125 Gbps with PRBS7 pattern and 20 dB loss channel.147mVpp
VIDlinearInput amplitude linear range. The maximum VID for which the repeater remains linear, defined as ≤1 dB compression of Vout/Vin.Measured with the highest wide-band gain setting (EQ_HIGH_GAIN = 1, DRV_SEL_VOD = 3). Measured with minimal input channel and minimum EQ using a 1 GHz signal.850mVpp
Measured with a mid wide-band gain setting (EQ_HIGH_GAIN = 1, DRV_SEL_VOD = 0). Measured with minimal input channel and minimum EQ using a 1 GHz signal.900mVpp
Measured with a mid wide-band gain setting (EQ_HIGH_GAIN = 0, DRV_SEL_VOD = 3). Measured with minimal input channel and minimum EQ using a 1 GHz signal.1050mVpp
Measured with the lowest wide-band gain setting (EQ_HIGH_GAIN = 0, DRV_SEL_VOD = 0). Measured with minimal input channel and minimum EQ using a 1 GHz signal.1250mVpp
HIGH-SPEED DIFFERENTIAL OUTPUTS (TXnP, TXnN)
VODidleDifferential output amplitude, TX disabled or otherwise muted< 10mVpp
GDCVout/Vin wide-band amplitude gainMeasured with the highest wide-band gain setting (EQ_HIGH_GAIN = 1, DRV_SEL_VOD = 3) at 20 MHz.4.5dB
Measured with the lowest wide-band gain setting (EQ_HIGH_GAIN = 0, DRV_SEL_VOD = 0) at 20 MHz.-5dB
Vcm-TX-ACCommon-mode AC output noiseDefined as (TXP + TXN)/2. Measured with a low-pass filter with 3 dB bandwidth at 33 GHz.6mV, RMS
Vcm-TX-DCCommon-mode DC outputDefined as (TXP + TXN)/2. Measured with a DC signal.0.750.961.05V
RJADD-RMSAdditive Random JitterMeasured as a single-ended signal on a Keysight E5505A phase noise measurement solution with a 28 Gbps 1010 pattern. Additive RJ measured over a frequency range of 2 kHz to 20 MHz.11fs RMS
RLSDD22Output differential-to-differential return loss50 MHz to 4.8 GHz< -16dB
4.8 GHz to 10 GHz< -15dB
10 GHz to 14.1 GHz< -8dB
14.1 GHz to 20 GHz< -8dB
RLSCD22Output common-mode-to-differential return loss50 MHz to 6.0 GHz< -21dB
6.0 GHz to 12.9 GHz< -22dB
12.9 GHz to 14.1 GHz< -21dB
14.1 GHz to 20 GHz< -20dB
RLSCC22Output Common-mode return loss50 MHz to 3.3 GHz< -13dB
3.3 GHz to 10.3 GHz< -11dB
10.3 GHz to 20 GHz< -9dB
OTHER PARAMETERS
tDInput-to-output latency (propagation delay) through a channelStraight-thru mode (no cross-point)100ps
tDInput-to-output latency (propagation delay) through a channelCross-over and mux mode (cross-point enabled)100ps
tSKChannel-to-channel interpair skewLatency difference between channels<14ps
TEEPROMEEPROM configuration load timeTime to assert ALL_DONE_N after REAN_EN_N has been asserted. Single device reading its configuration from an EEPROM with common channel configuration. This time scales with the number of devices reading from the same EEPROM. Does not include power-on reset time.4ms
Time to assert ALL_DONE_N after REAN_EN_N has been asserted. Single device reading its configuration from an EEPROM. Non-common channel configuration. This time scales with the number of devices reading from the same EEPROM. Does not include power-on reset time.7ms
TPORPower-on reset assertion timeInternal power-on reset (PoR) stretch between stable power supply and de-assertion of internal PoR. The SMBus address is latched on the completion of the PoR stretch, and SMBus accesses are permitted once PoR completes.60ms
(1) Max values assume VDD = 2.5 V + 5%.
(2) This pin has an internal weak pull-up.
(3) This pin has an internal weak pull-down.
Table 7-1 Electrical Characteristics – Serial Management Bus Interface
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VIHInput high level voltageSDA and SDC1.753.6V
VILInput low level voltageSDA and SDCGND0.8V
VOLOutput low level voltageSDA and SDC, IOL = 1.25 mAGND0.4V
CINInput pin capacitanceSDA and SDC15pF
IINInput currentSDA or SDC, VINPUT = VIN, VDD, GND-1818µA