SNLS542C October   2016  – December 2020 DS280MB810

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements – Serial Management Bus Interface
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Data Path Operation
      2. 8.3.2 AC-coupled Receiver Inputs
      3. 8.3.3 Signal Detect
      4. 8.3.4 2-Stage CTLE
      5. 8.3.5 Driver DC Gain Control
      6. 8.3.6 2x2 Cross-point Switch
      7. 8.3.7 Configurable SMBus Address
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Slave Mode Configuration
      2. 8.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 8.5 Programming
      1. 8.5.1 Transfer of Data with the SMBus Interface
    6. 8.6 Register Maps
      1. 8.6.1 Register Types: Global, Shared, and Channel
      2. 8.6.2 Global Registers: Channel Selection and ID Information
      3. 8.6.3 Shared Registers
      4. 8.6.4 Channel Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Reach Extension
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Front-Port Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Pattern Generator Characteristics
        2. 9.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 9.2.3.3 Equalizing High Pre-Channel Loss
        4. 9.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
    3. 9.3 Initialization Set Up
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 Stripline Example
      2. 11.2.2 Microstrip Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1 Layout Guidelines

The following guidelines should be followed when designing the layout:

  1. Decoupling capacitors should be placed as close to the VDD pins as possible. Placing them directly underneath the device is one option if the board design permits.
  2. High-speed differential signals should be tightly coupled, skew matched, and impedance controlled.
  3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, care should be taken to minimize the via stub, either by transitioning through most or all layers, or by back drilling.
  4. GND relief can be used beneath the high-speed differential signal pads to improve signal integrity by counteracting the pad capacitance.
  5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to the GND planes on other layers. This has the added benefit of improving thermal conductivity from the device to the board.
  6. BGA landing pads for a 0.8 mm pitch flip-chip BGA are typically 0.4 mm in diameter (exposed). The actual size of the copper pad will depend on whether solder-mask-defined (SMD) or non-solder-mask-defined solder land pads are used. For more information, refer to TI’s Surface Mount Technology (SMT) References website.