SNLS198B September   2005  – January 2019 DS90LV011AH

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Connection Diagram
      2.      Functional Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DS90LV011AH Driver Functionality
      2. 8.3.2 Driver Output Voltage and Power-On Reset
      3. 8.3.3 Driver Offset
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Driver Supply Voltage
        2. 9.2.2.2 Driver Bypass Capacitance
        3. 9.2.2.3 Driver Input Votlage
        4. 9.2.2.4 Driver Output Voltage
        5. 9.2.2.5 Interconnecting Media
        6. 9.2.2.6 PCB Transmission Lines
      3. 9.2.3 Termination Resistor
      4. 9.2.4 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Switching Characteristics

Over Supply Voltage and Operating Temperature Ranges, unless otherwise specified.(1)(2)(3)(4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPHLD Differential Propagation Delay High to Low RL = 100Ω, CL = 15 pF
(Figure 9 and Figure 10)
0.3 1 1.5 ns
tPLHD Differential Propagation Delay Low to High 0.3 1.1 1.5 ns
tSKD1 Differential Pulse Skew |tPHLD − tPLHD|(5) 0 0.1 0.7 ns
tSKD3 Differential Part to Part Skew(6) 0 0.2 1 ns
tSKD4 Differential Part to Part Skew(7) 0 0.4 1.2 ns
tTLH Transition Low to High Time 0.2 0.5 1 ns
tTHL Transition High to Low Time 0.2 0.5 1 ns
fMAX Maximum Operating Frequency(8) 200 250 MHz
All typicals are given for: VDD = +3.3V and TA = +25°C.
These parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage, temperature) ranges.
CL includes probe and fixture capacitance.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 1 ns, tf ≤ 1 ns (10%-90%).
tSKD1, |tPHLD − tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.
tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, VOD > 250mV. The parameter is specified by design. The limit is based on the statistical analysis of the device over the PVT range by the transitions times (tTLH and tTHL).