SNLS200B September   2005  – January 2019 DS90LV049H

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Dual-In-Line
      2.      Functional Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DS90LV049H LVDS Driver and Receiver Functionality
      2. 8.3.2 Termination
      3. 8.3.3 Fail-Safe Feature
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Decoupling Recommendations
        2. 9.2.2.2 PCB Transmission Lines
        3. 9.2.2.3 Input Fail-Safe Biasing
        4. 9.2.2.4 Probing LVDS Transmission Lines on PCB
        5. 9.2.2.5 Interconnecting Media
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

VDD = +3.3V ± 10%, TA = −40°C to +125°C(1)(9)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS Outputs (Driver Outputs)
tPHLD Differential Propagation Delay High to Low RL = 100 Ω
(Figure 3 and Figure 4)
0.7 2 ns
tPLHD Differential Propagation Delay Low to High 0.7 2 ns
tSKD1 Differential Pulse Skew |tPHLD − tPLHD|(2)(3) 0 0.05 0.4 ns
tSKD2 Differential Channel-to-Channel Skew(2)(4) 0 0.05 0.5 ns
tSKD3 Differential Part-to-Part Skew(2)(5) 0 1 ns
tTLH Rise Time(2) 0.2 0.4 1 ns
tTHL Fall Time(2) 0.2 0.4 1 ns
tPHZ Disable Time High to Z RL = 100 Ω
(Figure 5 and Figure 6)		 1.5 3 ns
tPLZ Disable Time Low to Z 1.5 3 ns
tPZH Enable Time Z to High 1 3 6 ns
tPZL Enable Time Z to Low 1 3 6 ns
fMAX Maximum Operating Frequency(10) 200 250 MHz
LVCMOS Outputs (Receiver Outputs)
tPHL Propagation Delay High to Low (Figure 7 and Figure 8) 0.5 2 3.5 ns
tPLH Propagation Delay Low to High 0.5 2 3.5 ns
tSK1 Pulse Skew |tPHL − tPLH|(6) 0 0.05 0.4 ns
tSK2 Channel-to-Channel Skew(7) 0 0.05 0.5 ns
tSK3 Part-to-Part Skew(8) 0 1 ns
tTLH Rise Time(2) 0.3 0.9 1.4 ns
tTHL Fall Time(2) 0.3 0.75 1.4 ns
tPHZ Disable Time High to Z (Figure 9 and Figure 10) 3 5.6 8 ns
tPLZ Disable Time Low to Z 3 5.4 8 ns
tPZH Enable Time Z to High 2.5 4.6 7 ns
tPZL Enable Time Z to Low 2.5 4.6 7 ns
fMAX Maximum Operating Frequency(11) 200 250 MHz
(1) All typical values are given for: VDD = +3.3 V, TA = +25°C.
(2) These parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage, temperature) ranges.
(3) tSKD1 or differential pulse skew is defined as |tPHLD − tPLHD|. It is the magnitude difference in the differential propagation delays between the positive going edge and the negative going edge of the same driver channel.
(4) tSKD2 or differential channel-to-channel skew is defined as the magnitude difference in the differential propagation delays between two driver channels on the same device.
(5) tSKD3 or differential part-to-part skew is defined as |tPLHD Max − tPLHD Min| or |tPHLD Max − tPHLD Min|. It is the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
(6) tSK1 or pulse skew is defined as |tPHL − tPLH|. It is the magnitude difference in the propagation delays between the positive going edge and the negative going edge of the same receiver channel.
(7) tSK2 or channel-to-channel skew is defined as the magnitude difference in the propagation delays between two receiver channels on the same device.
(8) tSK3 or part-to-part skew is defined as |tPLH Max − tPLH Min| or |tPHL Max − tPHL Min|. It is the difference between the minimum and maximum specified propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
(9) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
(10) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45%/55%, VOD > 250 mV, all channels switching.
(11) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, VID = 200 mV, VCM = 1.2 V . Output Criteria: duty cycle = 45%/55%, VOH > 2.7 V, VOL < 0.25 V, all channels switching.
(12) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.