SNLS407D April   2012  – October 2014 DS90UB925Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Recommended Timing for the Serial Control Bus
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Common Mode Filter Pin (CMF)
      5. 7.3.5  Video Control Signal Filter
      6. 7.3.6  EMI Reduction Features
        1. 7.3.6.1 Input SSC Tolerance (SSCT)
      7. 7.3.7  LVCMOS VDDIO Option
      8. 7.3.8  Power Down (PDB)
      9. 7.3.9  Remote Auto Power Down Mode
      10. 7.3.10 Input PCLK Loss Detect
      11. 7.3.11 Serial Link Fault Detect
      12. 7.3.12 Pixel Clock Edge Select (RFB)
      13. 7.3.13 Low Frequency Optimization (LFMODE)
      14. 7.3.14 Interrupt Pin — Functional Description And Usage (INTB)
      15. 7.3.15 Internal Pattern Generation
      16. 7.3.16 GPIO[3:0] and GPO_REG[8:4]
        1. 7.3.16.1 GPIO[3:0] Enable Sequence
        2. 7.3.16.2 GPO_REG[8:4] Enable Sequence
      17. 7.3.17 I2S Transmitting
        1. 7.3.17.1 Secondary I2S Channel
      18. 7.3.18 Built In Self Test (BIST)
        1. 7.3.18.1 BIST Configuration and Status
          1. 7.3.18.1.1 Sample BIST Sequence
        2. 7.3.18.2 Forward Channel And Back Channel Error Checking
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select (MODE_SEL)
      2. 7.4.2 Repeater Application
        1. 7.4.2.1 Repeater Configuration
        2. 7.4.2.2 Repeater Connections
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
    2. 9.2 CML Interconnect Guidelines
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from C Revision (April 2013) to D Revision

  • Added data sheet flow and layout to conform with new TI standards. Added the following sections: Handling Ratings, Device Functional Modes; Programming; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging and Ordering InformationGo
  • Added Device Information tableGo
  • Fixed typo for GPIO configurationGo
  • Removed two MODE_SEL modes: I2S Channel B, and Backward CompatibleGo
  • Removed IDx addresses 0x22, 0x24, 0x2E, 0x30, 0x32, 0x34Go
  • Changed suggested resistor values for IDx addresses 0x1E, 0x20, 0x26, 0x28, 0x2AGo

Changes from B Revision (August 2012) to C Revision

  • Changed layout of National datasheet to TI format.Go

Changes from A Revision (July 2012) to B Revision

  • Added typical charateristic graphicsGo
  • Added” Note: frequency range = 15 - 65MHz when LFMODE = 0 and frequency range = 5 - <15MHz when LFMODE = 1.” under Functional Description.Go
  • Reformatted Table 2 and added clarification to notes.Go
  • Added clarification to notes on Table 6, address 0x04[3:0] (backwards compatible and LFMODE registers). Go

Changes from * Revision (March 2012) to A Revision

  • Converted to hybrid TI format.Go
  • Corrected typo in SCL from pin 6 to pin 8.Go
  • Corrected typo in SDA from pin 7 to pin 9.Go
  • Added to Absolute Maximum Rating section, note (3): The maximum limit (VDDIO +0.3V) does not apply to the PDB pin during the transition to the power down state (PDB transitioning from HIGH to LOW)Go
  • Deleted derate from Maximum Power Dissipation Capacity at 25°C.Go
  • Added "Note: BIST is not available in backwards compatible mode."Go
  • Corrected typo in Table 4 "I2S Channel B (18-bit Mode)" from L to H Go
  • Corrected typo in Table 5 Ideal VR2(V) from 2.475 to 1.475. Go