SNLS479B NOVEMBER 2014 – May 2020 DS90UB940-Q1
PRODUCTION DATA.
The D_GPIO[3:0] pins can be configured to obtain different sampling rates depending on the mode as well as back channel frequency. The mode is controlled by register 0x43 (Register Maps). The back channel frequency can be controlled several ways:
The back channel frequency has variation of ±20%. Note: The back channel frequency must be set to 5 Mbps when paired with a DS90UB925Q-Q1, DS90UB925AQ-Q1, or DS90UB927Q-Q1. See Table 3 for details about configuring the D_GPIOs in various modes.
HSCC_MODE (0x43[2:0]) | MODE | NUMBER OF D_GPIOs | SAMPLES PER FRAME | D_GPIO EFFECTIVE FREQUENCY(1) (kHz) | D_GPIOs ALLOWED | ||
---|---|---|---|---|---|---|---|
5 Mbps BC(2) | 10 Mbps BC(3) | 20 Mbps BC(4) | |||||
000 | Normal | 4 | 1 | 33 | 66 | 133 | D_GPIO[3:0] |
011 | Fast | 4 | 6 | 200 | 400 | 800 | D_GPIO[3:0] |
010 | Fast | 2 | 10 | 333 | 666 | 1333 | D_GPIO[1:0] |
001 | Fast | 1 | 15 | 500 | 1000 | 2000 | D_GPIO0 |