SNLS477B October 2014 – November 2018 DS90UB948-Q1
DUAL_RX_CTL is described in Table 57.
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|6||RX_LOCK_MODE||R/W||0x0|| RX Lock Mode:
Determines operating conditions for indication of RX_LOCK and generation of video data.
0 : RX_LOCK asserted only when receiving active video (Forward channel VIDEO_DISABLED bit is 0)
1 : RX_LOCK asserted when device is linked to a Serializer even if active video is not being sent.
This allows indication of valid link where Bidirectional Control Channel is enabled, but Deserializer is not receiving Audio/Video data.
|5||RAW_2ND_BC||R/W||0x0|| Enable Raw Secondary Back channel
if this bit is set to a 1, the secondary back channel will operate in a raw mode, passing D_GPIO0 from the Deserializer to the Serializer, without any oversampling or filtering.
|4-3||FPD3_INPUT_MODE||R/W||0x0|| FPD-Link III Input Mode
Determines operating mode of dual FPD-Link III Receive interface
00: Auto-detect based on received data
01: Forced Mode: Dual link
10: Forced Mode: Single link, primary input
11: Forced Mode: Single link, secondary input
|1||PORT1_SEL||R/W||0x0|| Selects Port 1 for Register Access from primary I2C Address
For writes, port1 registers and shared registers will both be written.
For reads, port1 registers and shared registers will be read. This bit must be cleared to read port0 registers.
|0||PORT0_SEL||R/W||0x1|| Selects Port 0 for Register Access from primary I2C Address
For writes, port0 registers and shared registers will both be written.
For reads, port0 registers and shared registers will be read. Note that if PORT1_SEL is also set, then port1 registers will be read.