SNLS477B October 2014 – November 2018 DS90UB948-Q1
I2C_CONTROL_2 is described in Table 18.
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|7||FORWARD_CHANNEL_SEQUENCE_ERROR||R||0x0|| Control Channel Sequence Error Detected
This bit indicates a sequence error has been detected in forward control channel. If this bit is set, an error may have occurred in the control channel operation.
|6||CLEAR_SEQUENCE_ERROR||R/W||0x0||Clears the Sequence Error Detect bit|
|4-3||SDA_Output_Delay||R/W||0x0|| SDA Output Delay
This field configures output delay on the SDA output. Setting this value will increase output delay in units of 50ns. Nominal output delay values for SCL to SDA are:
|2||LOCAL_WRITE_DISABLE||R/W||0x0|| Disable Remote Writes to Local Registers
Setting this bit to a 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Deserializer registers from an I2C master attached to the Serializer. Setting this bit does not affect remote access to I2C slaves at the Deserializer.
|1||I2C_BUS_TIMER_SPEEDUP||R/W||0x0|| Speed up I2C Bus Watchdog Timer
1: Watchdog Timer expires after approximately 50 microseconds
0: Watchdog Timer expires after approximately 1 second.
|0||I2C_BUS_TIMER_DISABLE||R/W||0x0|| Disable I2C Bus Watchdog Timer
When the I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signalling occurs for approximately 1 second, the I2C bus will assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL