4 Revision History
Changes from Revision B (December 2018) to Revision C (January 2023)
- Updated the numbering format for tables, figures, and cross-references
throughout the document Go
- Changed all instances of legacy terminology to controller and
targetGo
- Revised the PDB pin voltage for normal operationGo
- Changed the VDD11 pin descriptions for clarityGo
- Added a link to Design Requirements under the RIN pinsGo
- Updated the VIH and VIL specifications of pins PDB,
XIN/REFCLK, and VDD_SELGo
- Removed the mention of CSI-2 non-synchronous clocking
modeGo
- Changed the bits that need to be modified for Clock Mode Go
- Changed the names of registers CAM_INT_RISE_STS and CAM_INT_FALL_STS to
SEN_INT_RISE_STS and SEN_INT_FALL_STS.Go
- Removed the mention of setting the REF_CLK_MODE bit as it is a
reserved bitGo
- Fixed typos in the internal FrameSync calculationsGo
- Rewrote the basic synchronized forwarding code example to set both
sensors to use CSI-2 serializersGo
- Added in that VVDDIO must match VI2C
Go
- Removed the mention of 'PDB' from register 0x0DGo
- Changed BCC_Config Register[2:0] binary setting value 0b111 to
reserved.Go
- Changed PORT_CONFIG2[5] default value to 0x1Go
- Changed suggested ferrite beads for 4G FPD-Link PoC Network from
1500 kΩ to 1.5 kΩ Go
- Changed PoC network impedance recommendation from 2kΩ to
1kΩGo
- Updated the PoC descriptionGo
- Removed the insertion and return loss values from the table on
Suggested Characteristics for Single-Ended PCB Traces With Attached PoC
NetworksGo
- Added a note to explain the differences between the decoupling
capacitorsGo
- Changed the pull-up resistor for PDB from 33-kΩ to 10-kΩGo
- Changed the value of the capacitor for pin VDD11_CSI from 1-μF to 10-μF in
the diagram where VDD_SEL = HIGHGo
- Moved the additional notes in the typical application diagram from the
picture to below the diagramGo
- Added a note to clarify the power-up sequence between VDD18 and
VDDIOGo
- Removed T0 and T2 from power-up sequenceGo
- Added a note to clarify that a hard reset is optional in the
power-up sequenceGo
- Added in T7, the PDB to I2C ready delay, to the power-up
sequenceGo
- Changed the pull-up resistor for PDB from 33-kΩ to 10-kΩGo
Changes from Revision A (September 2018) to Revision B (December 2018)
- Changed the intended content bandwidth limit from 2.528 Gbps to 3.328 Gbps Go
Changes from Revision * (August 2017) to Revision A (September 2018)
- Changed supply voltage test condition from V(VDD11)(VDD_SEL = LOW ONLY to V(VDD11)(VDD_SEL = HIGH ONLY) Go
- Added spread-spectrum reference clock modulation percentage parameter to the ROC tablesGo
- Added V(VDDIO) VDD18 ±50mV test condition to the high level output voltage parameterGo
- Added V(VDDIO) = VDD18 ±50mV test to the low level output voltage parameterGo
- Added PDB pin/frequency test condition and values to the high level input voltage parameterGo
- Added PDB pin/frequency test condition and values to the low level input voltage parameter Go
- Changed output short circuit current symbol from Isc to IosGo
- Added AEQ rating ±3ms RAW mode to the deserializer data lock time
parameterGo
- Added data bit rate minimum and typical values to the REFCLK = 23 MHz and REFCLK = 26 MHz test conditionsGo
- Added DDR clock frequency minmum and typical values to the REFCLK = 23 MHz and REFCLK = 26 MHz test conditionsGo
- Added the text '1.5 Gbps' after the 'Data rate <' and 'Data rate >' text in slew rate test conditions for falling and rising edgeGo
- Changed the UI instantaneous maximum value from 12.5 ns to 2.7 nsGo
- Added discrete synch signals requirement when using DVP format Go
- Changed FPD3_PCLK to fPCLK in the RAW mode line rate calculations Go
- Added information about YUV support Go
- Removed Coax/STP column and reorganized rows. Go
- Relaxed REFCLK Oscillator jitter specification to 200 ps maximum Go
- Relaxed REFCLK Oscillator rise and fall time to 6 ns maximum Go
- Added REFCLK spread-spectrum modulation percentage and frequency Go
- Changed Text from: AEQ_FLOOR value to: ADAPTIVE_EQ_FLOOR_VALUE Go
- Updated Forward Channel GPIO typical latency valueGo
- Updated Back Channel GPIO typical latency and jitter for 50 Mbps rateGo
- Added need for discrete synch signals in DVP mode and included RAW/YUV supportGo
- Changed from GPIO7 pin to GPIO6 pinGo
- Changed Text from: The total period of the FrameSync is (1 s / 60 hz) / 600 ns to: The total period of the FrameSync is (1 / 60 hz) / 600 nsGo
- Deleted Sentence "It is recommended to forward the relevant RX port data streams prior to enabling the CSI-2 TX output"Go
- Added Enabling and Disabling the CSI-2 Transmitter section Go
- Changed Sensor A and B to Sensor X in definition listGo
- Changed Node VDDIO to VI2C for SCL and SDA signal lines Go
- Changed Register 0x7C to register 0x7DGo
- Changed BIST_CTL to BIST Control to match register mapGo
- Changed Parity Error Threshold High to PAR_ERR_THOLD_HIGo
- Changed Parity Error Threshold Low to PAR_ERR_THOLD_LOGo
- Added Cross-reference to GPIO4_OUT_SRC bit descriptionGo
- Changed GPIO5_OUT_VAL bit description text from: GPIO5_OUT_SEL[2:0] = 00 to: GPIO5_OUT_SEL[2:0] = 000Go
- Changed GPIO6_OUT_VAL bit description text from: GPIO6_OUT_SEL[2:0] = 00 to: GPIO6_OUT_SEL[2:0] = 000Go
- Changed FS_GEN_MODE bit description text from: 'FS_HIGH_TIME and FS_LOW_TIME register values' to: 'FS_HIGH_TIME [15:0] and FS_LOW_TIME [15:0] register values' for clarityGo
- Changed INT bit to INTERRUPT_STS bit in INTERRUPT_STS bit descriptionGo
- Changed RESERVED bit numbers from: 6:4 to: 6:5Go
- Changed RESERVED bit description text from: CSI_PLL to: CSI_PLL_CTL Go
- Added sentence about RX port specific register for registers 0x4A, 0x4B, 0x4D - 0x7F, 0xD0 - 0xDF Go
- Updated RX_PORT_STS2 register bit 1 field and description Go
- Changed VOLT1_SENSE_LEVEL to VOLT0_SENSE_LEVELGo
- Changed PAR_ERROR line _BYTE_1 to PAR_ERROR _BYTE_1 and RX PARITY CHECKER ENABLE to RX_PARITY_CHECKER_ENABLEGo
- Changed RX PARITY CHECKER ENABLE to RX_PARITY_CHECKER_ENABLEGo
- Changed BCC_Config Register 0x58[2:0] binary setting value from 0b100 to 0b010 to select 10 Mbps non-synchronous back channel rate.Go
- Removed Text 'This field is normally loaded from the remote serializer. It can be overwritten if the OVERRIDE_FC_CONFIG bit in the DATAPATH_CTL0 register is 1.' from the RESERVED bit descriptionGo
- Changed PASSPARITY-ERR to PASS_PARITY_ERRGo
- Removed Broken link in the IND_ACC_CTL register tableGo
- Changed IA_SEL bit enumerations from: 0001-0100 and 1000-0111 to: 00011–0100 and 1000–1111Go
- Changed RESERVED Register to FPD3_ENC_CTL Go
- Changed RESERVED bit numbers from: 5:3 to: 4:2 Go
- Changed ADAPTIVE_EQ_FLOOR_VALUE bit description from: register {reg_35[5:4]} to: register 0xD2[2]Go
- Changed IE_FC_SENS_STS bit description from: Camera and CAM to: Sensor and SENGo
- Fixed Broken link in Power Over Coax sectionGo
- Redraw the PoC Network diagram Go
- Updated Return Loss S11 values Go
- Redraw RINx STP setting for figure "Typical Connection Diagram STP With
External 1.1-V supply"Go
- Fixed Broken links in the Detailed Design Procedure sectionGo
- Removed Second paragraph in System Examples
Go