SNLS589B September 2016 – July 2018 DS90UB960-Q1
The AEQ process steps through the allowed equalizer control values find a value that allows the Clock Data Recovery (CDR) circuit to keep a valid lock condition. The circuit waits for a programmed re-lock time period for each EQ setting, then the circuit checks the results for a valid lock. If a valid lock is detected, the circuit will stop at the current EQ setting and maintain a constant value as long as the lock state persists. If the deserializer loses the lock, the adaptive equalizer will resume the LOCK algorithm and the EQ setting is incremented to the next valid state. When the lock is lost, the circuit will search the EQ settings to find another valid setting to reacquire the serial data stream sent by the serializer that remains locked.