SNLS589B September 2016 – July 2018 DS90UB960-Q1
RX port specific register. The FPD-Link III Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.
|R/W||0x4||Time to wait for lock before incrementing the EQ to next setting
000 : 164 us
001 : 328 us
010 : 655 us
011 : 1.31 ms
100 : 2.62 ms
101 : 5.24 ms
110 : 10.5ms
111 : 21.0 ms
|R/W||1||AEQ First Lock Mode This register bit controls the Adaptive Equalizer algorithm operation at initial Receiver Lock.
0 : Initial AEQ lock may occur at any value
1 : Initial Receiver lock will restart AEQ at 0, providing a more deterministic initial AEQ value
|3||AEQ_RESTART||R/W/SC||0||Set high to restart AEQ adaptation from initial value. This bit is self clearing. Adaption is restarted.|
|2||SET_AEQ_FLOOR||R/W||1||AEQ adaptation starts from a pre-set floor value rather than from zero - good in long cable situations|