SNLS589B September 2016 – July 2018 DS90UB960-Q1
The AEQ circuit can be restarted at any time by setting the AEQ_RESTART bit in the AEQ_CTL2 register 0xD2 (See Table 184). When the deserializer is powered on, the AEQ is continually searching through the EQ settings and could be at any setting when signal is supplied from the serializer. If the Rx Port CDR locks to the signal, it may be good enough for low bit errors, but may not optimized or overequalized. When connected to a compatible serializer (DS90UB953-Q1, DS90UB933-Q1 or DS90UB913A-Q1), the DS90UB960-Q1 will restart the AEQ adaption by default after the device achieves the first positive lock indication to supply a more consistent start-up from known conditions.
With this feature disabled, the AEQ may lock at a relatively random EQ setting based on when the FPD-Link III input signal is initially present. Alternatively, AEQ_RESTART or DIGITAL_RESET0 can be applied once the compatible serializer input signal frequency is stable to restart adaption from the minimum EQ gain value. These techniques allow for a more consistent initial EQ setting following adaption.