SNLS589B September 2016 – July 2018 DS90UB960-Q1
CSI-2 TX port specific register. The CSI-2 Port Select register 0x32 configures which unique CSI-2 TX port registers can be accessed by I2C read and write commands.
|6||CSI_CAL_EN||R/W||0||Enable initial CSI-2 Skew-Calibration sequence
When the initial skew-calibration sequence is enabled, the CSI-2 Transmitter will send the sequence at initialization, prior to sending any HS data. This bit should be set when operating at 1.6 Gbps CSI-2 speed (as configured in the CSI_PLL register).
|5:4||CSI_LANE_COUNT||R/W||0x0||CSI-2 lane count
00: 4 lanes
01: 3 lanes
10: 2 lanes
11: 1 lane
|3:2||CSI_ULP||R/W||0||Force LP00 state on data/clock lanes
00: Normal operation
01: LP00 state forced only on data lanes
11: LP00 state forced on data and clock lanes
|1||CSI_CONTS_CLOCK||R/W||0||Enable CSI-2 continuous clock mode
NOTE: When enabled, the CSI-2 Transmitter will enter continuous clock mode upon transmission of the first packet
|0||CSI_ENABLE||R/W||0||Enable CSI-2 output
NOTE: Forwarding should be disabled (via the FWD_CTL1 register) prior to enabling or disabling the CSI-2 output.