SNLS589B September 2016 – July 2018 DS90UB960-Q1
For each FPD-Link III Receive port, multiple options are available for generating interrupts. Interrupt generation is controlled via the PORT_ICR_HI 0xD8 (Table 190) and PORT_ICR_LO 0xD9 (Table 191) registers. In addition, the PORT_ISR_HI 0xDA (Table 192) and PORT_ISR_LO 0xDB (Table 193) registers provide read-only status for the interrupts. Clearing of interrupt conditions is handled by reading the RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS registers. The status bits in the PORT_ISR_HI/LO registers are copies of the associated bits in the main status registers.
To enable interrupts from one of the Receive port interrupt sources:
To clear interrupts from one of the Receive port interrupt sources:
The first two steps are optional. The interrupt could be determined and cleared by just reading the status registers.