SNLS589B September 2016 – July 2018 DS90UB960-Q1
The general configuration register enables and disables high level block functionality.
|5||I2C_MASTER_EN||R/W||0||I2C Master Enable When this bit is 0, the local I2C master is disabled, when it is 1, the master is enabled.|
|4||OUTPUT_EN_MODE||R/W||1||Output Enable Mode
If set to 0, the CSI-2 TX output port is forced to the high-impedance state if no assigned RX ports have an active Receiver lock.
If set to 1, the CSI-2 TX output port will continue in normal operation if no assigned RX ports have an active Receiver lock. CSI-2 TX operation will remain under register control via the CSI_CTL register for each port. If no assigned RX ports have an active Receiver lock, this will result in the CSI-2 Transmitter entering the LP-11 state.
|3||OUTPUT_ENABLE||R/W||1||Output Enable Control (in conjunction with Output Sleep State Select)
If OUTPUT_SLEEP_STATE_SEL is set to 1 and this bit is set to 0, the CSI-2 TX outputs is forced into a high impedance state.
|R/W||1||OSS Select to control output state when LOCK is low (used in conjunction with Output Enable)
When this bit is set to 0, the CSI-2 TX outputs is forced into a HS-0 state.
|R/W||1||FPD3 Receiver Parity Checker Enable When enabled, the parity check function is enabled for the FPD3 receiver. This allows detection of errors on the FPD3 receiver data bits.
|0||FORCE_REFCLK_DET||R/W||0||Force indication of external reference clock
0: Normal operation, reference clock detect circuit indicates the presence of an external reference clock
1: Force reference clock to be indicated present