SNLS589B September 2016 – July 2018 DS90UB960-Q1
The DS90UB960-Q1 implements an I2C-compatible slave capable of operation compliant to the Standard, Fast, and Fast-plus modes of operation allowing I2C operation at up to 1-MHz clock frequencies. Local I2C transactions to access DS90UB960-Q1 registers can be conducted 2 ms after power supplies are stable and PDB is brought high. For accesses to local registers, the I2C Slave operates without stretching the clock. The primary I2C slave address is set through the IDx pin. The primary I2C slave address is stored in the I2C Device ID register at address 0x0. In addition to the primary I2C slave address, the DS90UB960-Q1 may be programmed to respond to up to four other I2C addresses. The four RX Port ID addresses provide direct access to the Receive Port registers without needing to set the paging controls normally required to access the port registers.