SNLS589B September 2016 – July 2018 DS90UB960-Q1
Several functional blocks include register sets contained in the Indirect Access map (Table 211); i.e. Pattern Generator, CSI-2 timing, and Analog controls. Register access is provided via an indirect access mechanism through the Indirect Access registers (IND_ACC_CTL, IND_ACC_ADDR, and IND_ACC_DATA). These registers are located at offsets 0xB0-0xB2 in the main register space.
The indirect address mechanism involves setting the control register to select the desired block, setting the register offset address, and reading or writing the data register. In addition, an auto-increment function is provided in the control register to automatically increment the offset address following each read or write of the data register.
For writes, the process is as follows:
If auto-increment is set in the IND_ACC_CTL register, repeating step 3 will write additional data bytes to subsequent register offset locations
For reads, the process is as follows:
If auto-increment is set in the IND_ACC_CTL register, repeating step 3 will read additional data bytes from subsequent register offset locations.
|IA Select 0xB0[5:2]||Page/Block||Indirect Registers||Address Range||Description|
|0000||0||Digital Page 0 Indirect Registers||0x01-0x1F||Pattern Gen Registers|
|0x40-0x51||CSI-2 TX port 0 Timing Registers|
|0x60-0x71||CSI-2 TX port 1 Timing Registers|
|0001||1||FPD3 Channel 0 Reserved Registers||0x00-0x14||Reserved|
|0010||2||FPD3 Channel 1 Reserved Registers||0x00-0x14||Reserved|
|0011||3||FPD3 Channel 2 Reserved Registers||0x00-0x14||Reserved|
|0100||4||FPD3 Channel 3 Reserved Registers||0x00-0x14||Reserved|
|0101||5||FPD3 Share Reserved Registers||0x00-0x04||Reserved|
|0110||6||Write All FPD3 Reserved Registers||0x00-0x14||Reserved|
|0111||7||CSI-2 TX Reserved Registers||0x00-0x1D||Reserved|