SNLS589B September 2016 – July 2018 DS90UB960-Q1
In Internal FrameSync mode, an internally generated FrameSync signal is sent to one or more of the attached FPD3 Serializers through a GPIO signal in the back channel.
FrameSync operation is controlled by the FS_CTL, FS_HIGH_TIME_x, and FS_LOW_TIME_x 0x18 – 0x1C registers (Table 45 through Table 49). The resolution of the FrameSync generator clock (FS_CLK_PD) is derived from the back channel frame period (BC_FREQ_SELECT register). For 50-Mbps back-channel operation, the frame period is 600 ns (30 bits × 20 ns/bit). For 2.5-Mbps back-channel operation, the frame period is 12 µs (30 bits × 400 ns/bit).
Once enabled, the FrameSync signal is sent continuously based on the programmed conditions.
Enabling the internal FrameSync mode is done by setting the FS_GEN_ENABLE control in the FS_CTL register to a value of 1. The FS_MODE field controls the clock source used for the FrameSync generation. The FS_GEN_MODE field configures whether the duty cycle of the FrameSync is 50/50 or whether the high and low periods are controlled separately. The FrameSync high and low periods are controlled by the FS_HIGH_TIME and FS_LOW_TIME registers.
The accuracy of the internally generated FrameSync is directly dependent on the accuracy of the 25-MHz oscillator used as the reference clock.
The following example shows generation of a FrameSync signal at 60 pulses per second. Mode settings:
Based on mode settings, the FrameSync is generated based upon FS_CLK_PD of 12 us.
The total period of the FrameSync is (1 sec / 60 hz) / 600 ns or approximately 27,778 counts.
For a 10% duty cycle, set the high time to 2,776 (0x0AD7) cycles, and the low time to 24,992 (0x61A0) cycles: