SNLS589B September 2016 – July 2018 DS90UB960-Q1
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the VQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP.
Example PCB layout is used to demonstrate both proper routing and proper solder techniques when designing in the Deserializer.
Figure 59 shows a PCB layout example are derived from the layout design of the DS90UB960-Q1EVM Evaluation Board. The graphic and layout description are used to determine proper routing when designing the board. The high speed FPD-Link III traces routed differentially up to the connector. A 100-Ω differential characteristic impedance and 50-Ω single-ended characteristic impedance traces are maintained as much as possible for both STP and coaxial applications. For the layout of a coaxial interconnects, coupled traces should be used with the RINx- termination near to the connector.