SNLS589B September 2016 – July 2018 DS90UB960-Q1
The PDB pin is active HIGH and must remain LOW while the VDD pin power supplies are in transition. An external RC network on the PDB pin may be connected to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDD18, a 10-kΩ pullup and a > 10-μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until both power supplies have reached steady state.
|tLRST||PDB Reset Low Pulse||2||ms|