SNLS589B September 2016 – July 2018 DS90UB960-Q1
The Raw modes provide FrameValid (FV) and LineValid (LV) controls for the video framing. The FV is equivalent to a Vertical Sync (VSYNC) while the LineValid is equivalent to a Horizontal Sync (HSYNC) input to the DS90UB913A-Q1 / DS90UB933-Q1 device.
The DS90UB960-Q1 allows setting the polarity of these signals by register programming. The FV and LV polarity are controlled on a per-port basis and can be independently set in the PORT_CONFIG2 register 0x7C (Table 141).
To prevent false detection of FrameValid, FV must be asserted for a minimum number of clocks prior to first video line to be considered valid. The minimum FrameValid time is programmable in the FV_MIN_TIME register 0xBC. Because the measurement is in FPD3 clocks, the minimum FrameValid setup to LineValid timing at the Serializer will vary based on operating mode.
A minimum FV to LV timing is required when processing video frames at the serializer input. If the FV to LV minimum setup is not met (by default), the first video line is discarded. Optionally, a register control (PORT_CONFIG:DISCARD_1ST_ON_ERR) forwards the first video line missing some number of pixels at the start of the line. There is no timing restrictions at the end of the frame.
(FV_MIN_TIME = 0)
(FV_MIN_TIME = 128)
For other settings of FV_MIN_TIME, the required FV to LV setup in Serializer PCLKs can be determined by:
Absolute Min + (FV_MIN_TIME * Conversion factor)