SNLS589B September 2016 – July 2018 DS90UB960-Q1
The DS90UB960-Q1 can support up to four simultaneous inputs to Rx ports 0 - 4. The Receiver port control register RX_PORT_CTL 0x0C (See Table 33) allows for disabling any Rx inputs when not in use. These bits can only be written by a local I2C master at the deserializer side of the FPD-Link.
Each FPD-Link III Receive port has a unique set of registers that provides control and status corresponding to Rx ports 0 - 4. Control of the FPD-Link III port registers is assigned by the FPD3_PORT_SEL register, which sets the page controls for reading or writing individual ports unique registers. For each of the FPD-Link III Receive Ports, the FPD3_PORT_SEL 0x4C register defaults to selecting that port’s registers as detailed in register description (See Table 93).
As an alternative to paging to access FPD-Link III Receive unique port registers, separate I2C addresses may be enabled to allow direct access to the port-specific registers. The Port I2C address registers 0xF8 - 0xFB allow programming a separate 7-bit I2C address to allow access to unique, port-specific registers without paging (See RX Port I2C Addressing Registers (Shared)). I2C commands to these assigned I2C addresses are also allowed access to all shared registers.