SNLS589B September 2016 – July 2018 DS90UB960-Q1
A valid 23-MHz to 26-MHz reference clock is required on the REFCLK pin 5 for precise frequency operation. The REFCLK frequency defines all internal clock timers, including the back channel rate, I2C timers, CSI-2 datarate, FrameSync signal parameters, and other timing critical internal circuitry. REFCLK input must be continuous. If the REFCLK input does not detect a transition more than 20 µs, this may cause a disruption in the CSI-2 output. REFCLK should be applied to the DS90UB960-Q1 only when the supply rails are above minimum levels (see Figure 56). At start-up, the DS90UB960-Q1 defaults to an internal oscillator to generate an backup internal reference clock at nominal frequency of 25 MHz ±10%.
As an option for mitigating EMI / EMC, the DS90UB960-Q1 is capable of tolerating a REFCLK with spread-spectrum clocking (SSC) profile with up to ±0.5% amplitude deviations (center spread) or up to 1% amplitude deviations (down spread) and up to 33 kHz frequency modulation from a clock source.
The REFCLK LVCMOS input oscillator specifications are listed in Table 3.
|Frequency tolerance with aging||–40ºC ≤ TA ≤ 105ºC, aging, no spread-spectrum||±100||ppm|
|Rise and fall time||10% – 90%||6||ns|
|Jitter||200 kHz – 10 MHz||50||200||ps p-p|
|Spread-spectrum clock modulation percentage (Optional)||Center spread||-0.5||+0.5||%|
|Spread-spectrum clock modulation frequency (Optional)||33||kHz|