SNLS589B September 2016 – July 2018 DS90UB960-Q1
RX port specific register. The FPD-Link III Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.
|7:0||PAR_ERROR_BYTE_0||R||0x0||Number of FPD3 parity errors – 8 least significant bits
The parity error counter registers return the number of data parity errors that have been detected on the FPD3 Receiver data since the last detection of valid lock or last read of the RX_PAR_ERR_LO register. For accurate reading of the parity error count, disable the RX PARITY CHECKER ENABLE bit in register 0x2 prior to reading the parity error count registers. This register is cleared on read.