SNLS589B September 2016 – July 2018 DS90UB960-Q1
RX port specific register. The FPD-Link III Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.
|7:6||RX_PORT_NUM||R||0x0||RX Port Number
This read-only field indicates the number of the currently selected RX read port.
|5||BCC_CRC_ERROR||R/RC||0||Bi-directional Control Channel CRC Error Detected
This bit indicates a CRC error has been detected in the forward control channel. If this bit is set, an error may have occurred in the control channel operation. This bit is cleared on read.
|4||LOCK_STS_CHG||R/RC||0||Lock Status Changed
This bit is set if a change in receiver lock status has been detected since the last read of this register. Current lock status is available in the LOCK_STS bit of this register
This bit is cleared on read.
|3||BCC_SEQ_ERROR / BCC_ERROR||R/RC // R||0||The function of this bit depends on the setting of the BCC_EN_ENH_ERR control in the BCC_ERR_CTL register.
If BCC_EN_ENH_ERR is 0 (disabled), this register is defined as follows: Bidirectional Control Channel Sequence Error Detected This bit indicates a sequence error has been detected in the forward control channel. If this bit is set, an error may have occurred in the control channel operation. This bit is cleared on read.
If BCC_EN_ENH_ERR is 1 (enabled), this register is defined as follows: Bidirectional Control Channel Error Flag This flag indicates one or more errors have been detected during Bidirectional Control Channel communication with the Deserializer. The BCC_STATUS register contains further information on the type of error detected. This bit will be cleared upon read of the BCC_STATUS register.
|2||PARITY_ERROR||R||0||FPD3 parity errors detected
This flag is set when the number of parity errors detected is greater than the threshold programmed in the PAR_ERR_THOLD registers.
1: Number of FPD3 parity errors detected is greater than the threshold
0: Number of FPD3 parity errors is below the threshold This bit is cleared when the RX_PAR_ERR_HI/LO registers are cleared.
|1||PORT_PASS||R||0||Receiver PASS indication This bit indicates the current status of the Receiver PASS indication. The requirements for setting the Receiver PASS indication are controlled by the PORT_PASS_CTL register.
1: Receive input has met PASS criteria
0: Receive input does not meet PASS criteria
|0||LOCK_STS||R||0||FPD-Link III receiver is locked to incoming data
1: Receiver is locked to incoming data
0: Receiver is not locked