SNLS543 August 2018 DS90UH949A-Q1
The Backward Channel provides bidirectional communication between the display and host processor. The information is carried from the deserializer to the serializer as serial frames. The back channel control data is transferred over both serial links along with the high-speed forward data, DC balance coding, and embedded clock information. This architecture provides a backward path across the serial link together with a high-speed forward channel. The back channel contains the I2C, HDCP, CRC, and 4 bits of standard GPIO information with a line rate of 5, 10, or 20 Mbps (configured by the compatible deserializer).