SNLS543 August 2018 DS90UH949A-Q1
The power supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB pin may be used to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDDIO, a 10-kΩ pull-up and a >10-μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until all power supplies have reached steady state.
The recommended power up sequence is as follows: VDD18, VTERM, VDD11, wait until all supplies have settled, activate PDB, then apply HDMI input. There will be no functional impact to using a different sequence than shown below, but the current draw on VTERM during power up may be higher in other cases.
The initialization sequence A shown in Figure 33 consists of any user defined device configurations and the following:
The initialization sequence B shown in Figure 33 should be performed after the HDMI clock has stabilized. Sequence B consists of the following:
VTERM must come before VDD18 When VTERM = 1.8V; this requirement is not applicable when VTERM = 3.3V.
The Init A and Init B sequence should consist of any user defined device configurations.
|VDD18, VDDIO||VDD18 / VDDIO voltage range||1.71||1.89||V|
|VTERM||VTERM voltage range||DC-coupled HDMI termination||3.135||3.465||V|
|AC-coupled HDMI termination||1.71||1.89||V|
|VDD11||VDD11 voltage range||1.045||1.155||V|
|VPDB_LOW||PDB LOW threshold
Note: VPDB should not exceed limit for respective I/O voltage before 90% voltage of VDD12
|VDDIO = 1.8V ± 5%||0.35 * VDDIO||V|
|VPDB_HIGH||PDB HIGH threshold||VDDIO = 1.8V ± 5%||0.65 * VDDIO||V|
|tr0||VTERM / VDDIO / VDD18 rise time||These time constants are specified for rise time of power supply voltage ramp (10% -90%).||1.5||ms|
|tr1||VDD11 rise time||These time constants are specified for rise time of power supply voltage ramp (10% -90%).||1.5||ms|
|t0||VDDIO / VDD18 delay time||VTERM needs to ramp-up before VDD18 and VDDIO.||0||ms|
|t1||VDD11 delay time||VDDIO and VDD18 need to ramp-up before VDD11.||0||ms|
|t2||PDB delay time||PDB should be released after all supplies are stable.||0||ms|
|t3||I2C ready time||Starting from PDB high, the local I2C access is available after this time.||2||ms|
|t4||Hard reset time||PDB negative pulse width required for the device reset.||2||ms|
|t5||PDB to HDMI delay time||Keep GPIOs low or high until after PDB release.||0||ms|
|t6||HDMI Clock Stable to PLL Reset (Init B)||HDMI Clock must be within 0.5% of the target frequency and stable.||1||µs|