SNLS543 August 2018 DS90UH949A-Q1
The SPI Control Channel uses the secondary link in a 2-lane FPD-Link III implementation. Two possible modes are available: Forward Channel and Reverse Channel modes. In Forward Channel mode, the SPI Master is located at the Serializer, such that the direction of sending SPI data is in the same direction as the video data. In Reverse Channel mode, the SPI Master is located at the Deserializer, such that the direction of sending SPI data is in the opposite direction as the video data.
The SPI Control Channel can operate in a high-speed mode when writing data, but must operate at lower frequencies when reading data. During SPI reads, data is clocked from the slave to the master on the SPI clock falling edge. Thus, the SPI read must operate with a clock period that is greater than the round-trip data latency. On the other hand, data for SPI writes can be sent at much higher frequencies where the MISO pin can be ignored by the master.
SPI data rates are not symmetrical for the two modes of operation. Data over the forward channel can be sent much faster than data over the reverse channel.
SPI cannot be used to access Serializer / Deserializer registers.