SNLS231O September   2006  – April 2015 DS90UR124-Q1 , DS90UR241-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Serializer Input Timing Requirements for TCLK
    7. 7.7 Serializer Switching Characteristics
    8. 7.8 Deserializer Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Initialization and Locking Mechanism
      2. 8.3.2  Data Transfer
      3. 8.3.3  Resynchronization
      4. 8.3.4  Powerdown
      5. 8.3.5  Tri-State
      6. 8.3.6  Pre-Emphasis
      7. 8.3.7  AC-Coupling and Termination
        1. 8.3.7.1 Receiver Termination Option 1
        2. 8.3.7.2 Receiver Termination Option 2
        3. 8.3.7.3 Receiver Termination Option 3
      8. 8.3.8  Signal Quality Enhancers
      9. 8.3.9  @SPEED-BIST Test Feature
      10. 8.3.10 Backward-Compatible Mode With DS90C241 and DS90C124
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using the DS90UR241 and DS90UR124
      2. 9.1.2 Display Application
      3. 9.1.3 Typical Application Connection
    2. 9.2 Typical Applications
      1. 9.2.1 DS90UR241-Q1 Typical Application Connection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Considerations
          2. 9.2.1.2.2 Noise Margin
          3. 9.2.1.2.3 Transmission Media
          4. 9.2.1.2.4 Live Link Insertion
        3. 9.2.1.3 Application Curves
      2. 9.2.2 DS90UR124 Typical Application Connection
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout and Power System Considerations
      2. 11.1.2 LVDS Interconnect Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (continued)

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.