SNLS231O September   2006  – April 2015 DS90UR124-Q1 , DS90UR241-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Serializer Input Timing Requirements for TCLK
    7. 7.7 Serializer Switching Characteristics
    8. 7.8 Deserializer Switching Characteristics
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Initialization and Locking Mechanism
      2. 8.3.2  Data Transfer
      3. 8.3.3  Resynchronization
      4. 8.3.4  Powerdown
      5. 8.3.5  Tri-State
      6. 8.3.6  Pre-Emphasis
      7. 8.3.7  AC-Coupling and Termination
        1. Receiver Termination Option 1
        2. Receiver Termination Option 2
        3. Receiver Termination Option 3
      8. 8.3.8  Signal Quality Enhancers
      9. 8.3.9  @SPEED-BIST Test Feature
      10. 8.3.10 Backward-Compatible Mode With DS90C241 and DS90C124
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using the DS90UR241 and DS90UR124
      2. 9.1.2 Display Application
      3. 9.1.3 Typical Application Connection
    2. 9.2 Typical Applications
      1. 9.2.1 DS90UR241-Q1 Typical Application Connection
        1. Design Requirements
        2. Detailed Design Procedure
          1. Power Considerations
          2. Noise Margin
          3. Transmission Media
          4. Live Link Insertion
        3. Application Curves
      2. 9.2.2 DS90UR124 Typical Application Connection
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout and Power System Considerations
      2. 11.1.2 LVDS Interconnect Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The DS90UR241 Serializer and DS90UR124 Deserializer chipset is an easy-to-use transmitter and receiver pair that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 120 Mbps to 1.03 Gbps throughput. The DS90UR241 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS serial data stream with embedded clock and scrambles / DC Balances the data to enhance signal quality to support AC coupling. The DS90UR124 receives the LVDS serial data stream and converts it back into a 24-bit wide parallel data and recovered clock. The 24-bit Serializer/Deserializer chipset is designed to transmit data up to 10 meters over shielded twisted pair (STP) at clock speeds from 5 MHz to 43 MHz.

The Deserializer can attain lock to a data stream without the use of a separate reference clock source, greatly simplifying system complexity and overall cost. The Deserializer synchronizes to the Serializer regardless of data pattern, delivering true automatic “plug and lock” performance. It will lock to the incoming serial stream without the need of special training patterns or sync characters. The Deserializer recovers the clock and data by extracting the embedded clock information and validating data integrity from the incoming data stream and then deserializes the data. The Deserializer monitors the incoming clock information, determines lock status, and asserts the LOCK output high when lock occurs.

In addition, the Deserializer also supports an optional @SPEED BIST (Built In Self Test) mode, BIST error flag, and LOCK status reporting pin. Signal quality on the wide parallel output is controlled by the SLEW control and bank slew (PTOSEL) inputs to help reduce noise and system EMI. Each device has a power down control to enable efficient operation in various applications.

8.2 Functional Block Diagram

DS90UR124-Q1 DS90UR241-Q1 20194501.gif

8.3 Feature Description

8.3.1 Initialization and Locking Mechanism

Initialization of the DS90UR241 and DS90UR124 must be established before each device sends or receives data. Initialization refers to synchronizing the Serializer’s and Deserializer’s PLL’s together. After the Serializers locks to the input clock source, the Deserializer synchronizes to the Serializers as the second and final initialization step.

Step 1: When VDD is applied to both Serializer and/or Deserializer, the respective outputs are held in Tri-state and internal circuitry is disabled by on-chip power-on circuitry. When VDD reaches VDD OK (approximately 2.2 V) the PLL in Serializer begins locking to a clock input. For the Serializer, the local clock is the transmit clock, TCLK. The Serializer outputs are held in Tri-state while the PLL locks to the TCLK. After locking to TCLK, the Serializer block is now ready to send data patterns. The Deserializer output will remain in Tri-state while its PLL locks to the embedded clock information in serial data stream. Also, the Deserializer LOCK output will remain low until its PLL locks to incoming data and sync-pattern on the RIN± pins.

Step 2: The Deserializer PLL acquires lock to a data stream without requiring the Serializer to send special patterns. The Serializer that is generating the stream to the Deserializer will automatically send random (non-repetitive) data patterns during this step of the Initialization State. The Deserializer will lock onto embedded clock within the specified amount of time. An embedded clock and data recovery (CDR) circuit locks to the incoming bit stream to recover the high-speed receive bit clock and re-time incoming data. The CDR circuit expects a coded input bit stream. In order for the Deserializer to lock to a random data stream from the Serializer, it performs a series of operations to identify the rising clock edge and validates data integrity, then locks to it. Because this locking procedure is independent on the data pattern, total random locking duration may vary. At the point when the Deserializer’s CDR locks to the embedded clock, the LOCK pin goes high and valid RCLK/data appears on the outputs. Note that the LOCK signal is synchronous to valid data appearing on the outputs. The Deserializer’s LOCK pin is a convenient way to ensure data integrity is achieved on receiver side.

8.3.2 Data Transfer

After Serializer lock is established, the inputs DIN0–DIN23 are used to input data to the Serializer. Data is clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The Serializer outputs (DOUT±) are intended to drive point-to-point connections.

CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream (Figure 30). The CLK1 bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded clock bits in the serial stream. DCB functions as the DC Balance control bit. It does not require any pre-coding of data on transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal lines. This bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to validate data integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and automatically performed within Serializer and Deserializer.

The chipset supports clock frequency ranges of 5 MHz to 43 MHz. Every clock cycle, 24 databits are sent along with 4 additional overhead control bits. Thus the line rate is 1.20 Gbps maximum (140Mbps minimum). The link is extremely efficient at 86% (24/28). Twenty five (24 data + 1 clock) plus associated ground signals are reduced to only 1 single LVDS pair providing a compression ratio of better then 25 to 1.

In the serialized data stream, data/embedded clock & control bits (24+4 bits) are transmitted from the Serializer data output (DOUT±) at 28 times the TCLK frequency. For example, if TCLK is 43 MHz, the serial rate is 43 × 28 = 1.20 Giga bits per second. Since only 24 bits are from input data, the serial “payload” rate is 24 times the TCLK frequency. For instance, if TCLK = 43 MHz, the payload data rate is 43 x 24 = 1.03 Gbps. TCLK is provided by the data source and must be in the range of 5 MHz to 43 MHz nominal. The Serializer outputs (DOUT±) can drive a point-to-point connection as shown in Figure 29. The outputs transmit data when the enable pin (DEN) is high and TPWDNB is high. The DEN pin may be used to Tri-state the outputs when driven low.

When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin. The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high, data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the RRFB input. ROUT[23:0], LOCK and RCLK outputs will each drive a maximum of 4-pF load with a 43-MHz clock. REN controls Tri-state for ROUTn and the RCLK pin on the Deserializer.

8.3.3 Resynchronization

If the Deserializer loses lock, it will automatically try to re-establish lock. For example, if the embedded clock edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The Deserializer then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock edge, identifies it, and then proceeds through the locking process.

The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid. The system may monitor the LOCK pin to determine whether data on the ROUT is valid.

8.3.4 Powerdown

The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into powerdown mode, which reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is driven low. In powerdown, the PLL stops and the outputs go into Tri-state, disabling load current and reducing current supply. To exit Powerdown, TPWDNB must be driven high. When the Serializer exits Powerdown, its PLL must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization before data transfer can begin. The Deserializer enters powerdown mode when RPWDNB is driven low. In powerdown mode, the PLL stops and the outputs enter Tri-state. To bring the Deserializer block out of the powerdown state, the system drives RPWDNB high.

Both the Serializer and Deserializer must reinitialize and relock before data can be transferred. The Deserializer will initialize and assert LOCK high when it is locked to the embedded clock.

8.3.5 Tri-State

For the Serializer, Tri-state is entered when the DEN or TPWDNB pin is driven low. This will Tri-state both driver output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer will return to the previous state as long as all other control pins remain static (TPWDNB, TRFB).

When you drive the REN or RPWDNB pin low, the Deserializer enters Tri-state. Consequently, the receiver output pins (ROUT0–ROUT23) and RCLK will enter Tri-state. The LOCK output remains active, reflecting the state of the PLL. The Deserializer input pins are high impedance during receiver powerdown (RPWDNB low) and power-off (VDD = 0 V).

8.3.6 Pre-Emphasis

The DS90UR241 features a Pre-Emphasis function used to compensate for long or lossy transmission media. Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output current during transitions to counteract cable loading effects. The transmission distance will be limited by the loss characteristics and quality of the media. Pre-Emphasis adds extra current during LVDS logic transition to reduce the cable loading effects and increase driving distance. In addition, Pre-Emphasis helps provide faster transitions, increased eye openings, and improved signal integrity. The ability of the DS90UR241 to use the Pre-Emphasis feature will extend the transmission distance up to 10 meters in most cases.

To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to Vss in order to set the additional current level. Values of Rpre should be between 6 kΩ and 100 MΩ. Values less than 6 kΩ should not be used. A lower input resistor value on the ”PRE” pin increases the magnitude of dynamic current during data transition. The additional source current is based on the following formula: PRE = (RPRE ≥ 6 kΩ); IMAX = [48 / RPRE]. For example if Rpre = 15 kΩ , then the Pre-Emphasis current is increase by an additional 3.2 mA.

The amount of Pre-Emphasis for a given media will depend on the transmission distance of the application. In general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This can result in excessive noise, crosstalk and increased power dissipation. For short cables or distances, Pre-Emphasis may not be required. Signal quality measurements are recommended to determine the proper amount of Pre-Emphasis for each application.

8.3.7 AC-Coupling and Termination

The DS90UR241 and DS90UR124 supports AC-coupled interconnects through integrated DC balanced encoding/decoding scheme. To use the Serializer and Deserializer in an AC-coupled application, insert external AC-coupling capacitors in series in the LVDS signal path as illustrated in Figure 29. The Deserializer input stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal VCM to +1.8V. With AC signal coupling, capacitors provide the AC-coupling path to the signal input.

For the high-speed LVDS transmissions, the smallest available package should be used for the AC-coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. The most common used capacitor value for the interface is a 100 nF (0.1 uF). NPO class 1 or X7R class 2 type capacitors are recommended. 50 WVDC should be the minimum used for the best system-level ESD performance.

A termination resistor across DOUT± and RIN± is also required for proper operation to be obtained. The termination resistor should be equal to the differential impedance of the media being driven. This should be in the range of 90 to 132 Ω. 100 Ω is a typical value common used with standard 100-Ω transmission media. This resistor is required for control of reflections and also completes the current loop. It should be placed as close to the Serializer DOUT± outputs and Deserializer RIN± inputs to minimize the stub length from the pins. To match with the deferential impedance on the transmission line, the LVDS I/O are terminated with 100-Ω resistors on Serializer DOUT± outputs pins and Deserializer RIN± input pins. Receiver Termination Option 1

A single 100-Ω termination resistor is placed across the RIN± pins (see Figure 29). This provides the signal termination at the Receiver inputs. Other options may be used to increase noise tolerance. Receiver Termination Option 2

For additional EMI tolerance, two 50-Ω resistors may be used in place of the single 100-Ω resistor. A small capacitor is tied from the center point of the 50-Ω resistors to ground (see Figure 31). This provides a high-frequency low impedance path for noise suppression. Value is not critical, 4.7 nF may be used with general applications. Receiver Termination Option 3

For high noise environments, an additional voltage divider network may be connected to the center point. This has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the range of 100Ω-2KΩ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.8 V. For example (see Figure 32): VDD=3.3 V, Rpullup=1 KΩ, Rpulldown=1.2 KΩ; or Rpullup=100 Ω, Rpulldown=120 Ω (strongest). The smaller values will consume more bias current, but will provide enhanced noise suppression.

8.3.8 Signal Quality Enhancers

The DS90UR124 Deserializer supports two signal quality enhancers. The SLEW pin is used to increase the drive strength of the LVCMOS outputs when driving heavy loads. SLEW allows output drive strength for high or low current drive. Default setting is LOW for low drive at 2 mA and HIGH for high drive at 4 mA.

There are two types of Progressive Turnon modes (Fixed and PTO Frequency Spread) to help reduce EMI: simultaneous switching noise and system ground bounce. The PTOSEL pin introduces bank skew in the data/clock outputs to limit the number of outputs switching simultaneously. For Fixed-PTO mode, the Deserializer ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 2 or 1 UI apart in phase from RCLK for Group 1 and Groups 2, 3, respectively (see Figure 17). In the PTO Frequency Spread mode, ROUT[23:0] are also grouped into three groups of eight, with each group is separated out of phase with the adjacent groups (see Figure 18) per every 4 cycles. Note that in the PTO Frequency Spread operating mode RCLK is also spreading and separated by 1 UI.

8.3.9 @SPEED-BIST Test Feature

To assist vendors with test verification, the DS90UR241 and DS90UR124 is equipped with built-in self-test (BIST) capability to support both system manufacturing and field diagnostics. BIST mode is intended to check the entire high-speed serial link at full link-speed, without the use of specialized and expensive test equipment. This feature provides a simple method for a system host to perform diagnostic testing of both Serializer and Deserializer. The BIST function is easily configured through the 2 control pins on the DS90UR124. When the BIST mode is activated, the Serializer has the ability to transfer an internally generated PRBS data pattern. This pattern traverses across interconnecting links to the Deserializer. The DS90UR124 includes an on-chip PRBS pattern verification circuit that checks the data pattern for bit errors and reports any errors on the data output pins on the Deserializer.

The @SPEED-BIST feature uses 2 signal pins (BISTEN and BISTM) on the DS90UR124 Deserializer. The BISTEN and BISTM pins together determine the functions of the BIST mode. The BISTEN signal (HIGH) activates the test feature on the Deserializer. After the BIST mode is enabled, all the data input channels DIN[23:0] on the DS90UR241 Serializer must be set logic LOW or floating in order for Deserializer to start accepting data. An input clock signal (TCLK) for the Serializer must also be applied during the entire BIST operation. The BISTM pin selects error reporting status mode of the BIST function. When BIST is configured in the error status mode (BISTM = LOW), each of the ROUT[23:0] outputs will correspond to bit errors on a cycle-by-cycle basis. The result of bit mismatches are indicated on the respective parallel inputs on the ROUT[23:0] data output pins. In the BIST error-count accumulator mode (BISTM = HIGH), an 8-bit counter on ROUT[7:0] is used to represent the number of errors detected (0 to 255 max). The successful completion of the BIST test is reported on the PASS pin on the Deserializer. The Deserializer's PLL must first be locked to ensure the PASS status is valid. The PASS status pin will stay LOW and then transition to HIGH once a BER of 1x10-9 is achieved across the transmission link.

8.3.10 Backward-Compatible Mode With DS90C241 and DS90C124

The RAOFF pin allows a backward-compatible mode with DS90C241 and DS90C124 devices. To interface with either DS90C241 Serializer or DS90C124 Deserializer, the RAOFF pin on DS90UR241 or DS90UR124 must be tied HIGH to disable the additional LSFR coding. For normal operation directly with DS90UR241 to DS90UR124, RAOFF pins are set LOW. See Table 1 and Table 2 for more details.

8.4 Device Functional Modes

Table 1. DS90UR241 Serializer Truth Table

(Pin 9)
(Pin 18)
(Pin 12)
Tx PLL Status
LVDS Outputs
(Pins 19 and 20)
L X X X Hi-Z
H L X X Hi-Z
H H X Not Locked Hi-Z
H H L Locked Serialized Data with Embedded Clock (DS90UR124 compatible)
H H H Locked Serialized Data with Embedded Clock (DS90C124 compatible)

Table 2. DS90UR124 Deserializer Truth Table

(Pin 48)
(Pin 60)
(Pin 63)
Rx PLL Status
(See Pin Diagram)
(Pin 23)
L X X X Hi Z Hi Z
H L X X Hi Z L = PLL Unocked;
H = PLL Locked
H H X Not Locked Hi Z L
H H L Locked Data and RCLK Active (DS90UR241 compatible) H
H H H Locked Data and RCLK Active (DS90C241 compatible) H