SNLS346C
August 2011 – June 2014
DS90UR903Q-Q1
,
DS90UR904Q-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Handling Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Recommended Serializer Timing for PCLK
6.7
Serial Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (See )
6.8
Serial Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
6.9
Serializer Switching Characteristics
6.10
Deserializer Switching Characteristics
6.11
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.2.1
Typical Application Diagram
7.2.2
Block Diagrams
7.3
Feature Description
7.3.1
Serial Frame Format
7.3.2
Signal Quality Enhancers
7.3.2.1
Des - Receiver Input Equalization (EQ)
7.3.3
Emi Reduction
7.3.3.1
Des - Receiver Staggered Output
7.3.3.2
Des Spread Spectrum Clocking
7.4
Device Functional Modes
7.4.1
LVCMOS VDDIO Option
7.4.2
Powerdown
7.4.3
Pixel Clock Edge Select (TRFB/RRFB)
7.5
Programming
7.5.1
Description of Serial Control Bus
7.5.2
ID[X] Address Decoder
7.6
Register Maps
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Typical Application Connection
8.2.2.2
AC Coupling
8.2.2.3
Power Up Requirements and PDB PIN
8.2.2.4
Transmission Media
8.2.2.5
Serial Interconnect Guidelines
8.2.2.6
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Related Links
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTA|40
MPQF134A
Thermal pad, mechanical data (Package|Pins)
RTA|40
QFND447B
Orderable Information
snls346c_oa
snls346c_pm