SLVSE49A July   2017  – July 2017 ESD401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings — JEDEC Specification 
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 ESD Protection
      2. 7.3.2 IEC 61000-4-4 EFT Protection
      3. 7.3.3 IEC 61000-4-5 Surge Protection
      4. 7.3.4 IO Capacitance
      5. 7.3.5 DC Breakdown Voltage
      6. 7.3.6 Low Leakage Current
      7. 7.3.7 Low ESD Clamping Voltage
      8. 7.3.8 Industrial Temperature Range
      9. 7.3.9 Industry Standard Footprint
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Electrical fast transient IEC 61000-4-4 (5/50 ns) at 25°C 80 A
Peak pulse IEC 61000-4-5 power (tp - 8/20 µs) at 25°C 67 W
IEC 61000-4-5 current (tp - 8/20 µs) at 25°C 4.5 A
TA Operating free-air temperature –40 125 °C
Tstg Storage temperature –65 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings — JEDEC Specification 

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings—IEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±24000 V
IEC 61000-4-2 air-gap discharge ±30000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIO Input pin voltage –5.5 5.5 V
TA Operating free-air temperature –40 125 °C

6.5 Thermal Information

THERMAL METRIC(1) ESD401 UNIT
DPY (X1SON)
2 PINS
RθJA Junction-to-ambient thermal resistance 420 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 169.3 °C/W
RθJB Junction-to-board thermal resistance 276.1 °C/W
ψJT Junction-to-top characterization parameter 122.1 °C/W
ψJB Junction-to-board characterization parameter 157.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 nA –5.5 5.5 V
VBRF Breakdown voltage, Pin 1 to Pin 2 (1) IIO =1 mA, at TA = 25°C 7.5 9.1 V
VBRR Breakdown voltage, Pin 2 to Pin 1 (1) IIO =1 mA, at TA = 25°C 7.5 9.1 V
VHOLD Holding voltage (2) IIO =1 mA 8.3 V
VCLAMP Clamping voltage IPP = 1 A, TLP, from Pin 1 to Pin 2 and Pin 2 to Pin 1, TA = 25°C 11 V
IPP = 5 A, TLP, from Pin 1 to Pin 2 and Pin 2 to Pin 1, TA = 25°C 16
IPP = 16 A, TLP, from Pin 1 to Pin 2 and Pin 2 to Pin 1, TA = 25°C 24
IPP = 1.8 A, IEC-61000-4-5 (tp - 8/20 µs) from Pin 1 to Pin 2 and Pin 2 to Pin 1, TA = 25°C 12
IPP = 4.5 A, IEC-61000-4-5 (tp - 8/20 µs) from Pin 1 to Pin 2 and Pin 2 to Pin 1, TA = 25°C 15
ILEAK Leakage current, Pin 1 to Pin2 and PIn2 to Pin 1 VIO = ±2.5 V 0.03 10 nA
RDYN Dynamic resistance Measured between TLP IPP of 10 A and 20 A, Pin 2 to Pin 1 and Pin 1 to Pin2, TA = 25°C 0.7 Ω
CL Line capacitance VIO = 0 V, f = 1 MHz, Pin 1 to Pin 2 and Pin2 to Pin1, TA = 25°C 0.77 0.95 pF
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state.
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.

6.7 Typical Characteristics

ESD401 D001_SLVSE49.gif Figure 1. Positive TLP Curve, Pin 1 to Pin 2
ESD401 D003_SLVSE49.gif Figure 3. 8-kV IEC 61000-4-2 Waveform, Pin1 to Pin 2
ESD401 D005_SLVSE49.gif Figure 5. Surge (IEC 61000-4-5) Curve (tp = 8/20 µs), Pin 1 to Pin 2
ESD401 D007_SLVSE49.gif Figure 7. DC Voltage Sweep I-V Curve, Pin 1 to Pin 2
ESD401 D009_SLVSE49.gif Figure 9. Insertion Loss
ESD401 D002_SLVSE49.gif Figure 2. Negative TLP Curve, Pin 1 to Pin 2 (Plotted as Positive TLP Curve Pin 2 to Pin 1
ESD401 D004_SLVSE49.gif Figure 4. –8-kV IEC 61000-4-2 Waveform, Pin 1 to Pin 2
ESD401 D006_SLVSE49.gif Figure 6. Capacitance vs Bias Voltage, Pin 1 to Pin 2
ESD401 D008_SLVSE49.gif Figure 8. Leakage Current vs. Temperature, Pin 1 to Pin 2
ESD401 D010_SLVSE49.gif Figure 10. Capacitance vs. Frequency, Pin 1 to Pin 2