SLVSGX0 May   2022 ESD752

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—JEDEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 AEC-Q101 Qualified and Temperature Range
      2. 7.3.2 IEC 61000-4-5 Surge Protection
      3. 7.3.3 IO Capacitance
      4. 7.3.4 Dynamic Resistance
      5. 7.3.5 DC Breakdown Voltage
      6. 7.3.6 Ultra Low Leakage Current
      7. 7.3.7 Clamping Voltage
      8. 7.3.8 Industry Standard Leaded Packages
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCK|3
  • DBZ|3
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

over TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS DEVICE MIN TYP MAX UNIT
VRWM Reverse stand-off voltage ESD752 –24 24 V
VBRF Forward breakdown voltage IIO = 1 mA, any IO pin to GND(1) ESD752 25.5 27.5 29.5 V
VBRR Reverse breakdown voltage IIO = –1 mA, any IO pin to GND(1) ESD752 –29.5 -27.5 –25.5 V
VCLAMP Clamping voltage(3) IPP = 6 A, tp = 8/20 µs, from IO to GND ESD752 31 42 V
Clamping voltage(4) IPP = 16 A, TLP, from IO to GND 33
VHold Holding voltage after snapback(2) ESD752 28.5 V
ILEAK Leakage current VIO = ±24 V, any IO pin to GND ESD752 -50 1 50 nA
RDYN Dynamic resistance(4) IO to GND, (Pin 1 or Pin 2 to Pin 3) ESD752 0.35 Ω
GND to IO (Pin 3 to Pin 1 or Pin 2) 0.35
CL Line capacitance, any IO to GND VIO = 0 V, f = 1 MHz, Vp-p = 30 mV ESD752 3 5 pF
VIO = 2.5 V, f = 1 MHz, Vp-p = 30 mV 2.5 5 pF
VBRF and VBRR are defined as the voltage when 1 mA is applied in the positive-going direction, before the device latches into the snapback state.
VHOLD is defined as the voltage when 1 mA is applied in the negative-going direction, after the device has successfully latched into the snapback state.
Device stressed with 8/20 μs exponential decay waveform according to IEC 61000-4-5.
Non-repetitive current pulse, Transmission Line Pulse (TLP); square pulse; ANSI / ESD STM5.5.1-2008