SLVSEG9B May   2018  – September 2018 ESDS312 , ESDS314

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Typical Application Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions for ESDS312
    2.     Pin Functions for ESDS314
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings -JEDEC Specifications
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-4 EFT Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 500 nA, across operating temperature range 3.6 V
ILEAKAGE Leakage current at 3.6 V VIO = 3.6 V, Any IO pin to GND 5 50 nA
VBRF Breakdown voltage, IO to GND (1) IIO = 1 mA 4.5 7.5 V
VFWD Forward Voltage, GND to IO IIO = 1 mA 0.8 V
VHOLD Holding Voltage, IO to GND (2) IIO = 1 mA 5 V
VCLAMP Surge Clamping voltage, tp = 8/20 µs IPP = 1 A, Any IO pin to GND 5 V
VCLAMP IPP = 12 A, Any IO pin to GND 5.6 V
VCLAMP IPP = 25 A, Any IO pin to GND 6.5 V
VCLAMP IPP = 1 A, GND to any IO pin 1 V
VCLAMP IPP = 12 A, GND to any IO pin 2.1 V
VCLAMP IPP = 25 A, GND to any IO pin 3.6 V
VCLAMP TLP Clamping Voltage, tp = 100 ns IPP = 16 A, Any IO pin to GND 5.5 V
VCLAMP IPP = 16 A, GND to any IO pin 2.2 V
CLINE Line capacitance, Any IO to GND VIO = 0 V, Vp-p = 30 mV, f = 1 MHz 4.5 5.5 pF
ΔCLINE Variation of line capacitance CLINE1 - CLINE2, VIO = 0 V, Vp-p = 30 mV, f = 1 MHz 0.05 0.1 pF
CCROSS Line-to-line capacitance VIO = 0V, Vrms = 30 mV, f = 1 MHz 2.25 2.75 pF
VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state
VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.