SLVSEG9B May   2018  – September 2018 ESDS312 , ESDS314

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Typical Application Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions for ESDS312
    2.     Pin Functions for ESDS314
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings -JEDEC Specifications
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-4 EFT Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

ESDS312 ESDS314 D001_SLVSEG9.gif
Figure 1. Clamping Voltage vs. Peak Pulse Current (tp= 8/20 µs), Any IO Pin to GND
ESDS312 ESDS314 D003_SLVSEG9.gif
Figure 3. Surge Current, Clamping Voltage and Power Curve (tp = 8/20 µs), Any IO Pin to GND
ESDS312 ESDS314 D005_TLP_Pos.gif
Figure 5. TLP I-V Curve, IO to GND, tp = 100 ns
ESDS312 ESDS314 D007_IEC_Pos.gif
Figure 7. +8 kV IEC 61000-4-2 Clamping Voltage Waveform
ESDS312 ESDS314 D009_Leakage.gif
Figure 9. DC Leakage vs. Ambient Temperature, Bias Voltage = 3.6 V
ESDS312 ESDS314 D011_Power_Derating.gif
Figure 11. Surge Power Derating with Respect To Ambient Temperature
ESDS312 ESDS314 D002_SLVSEG9.gif
Figure 2. Clamping Voltage vs. Peak Pulse Current (tp= 8/20 µs), GND to Any IO Pin
ESDS312 ESDS314 D004_DC_Plot.gif
Figure 4. DC I-V Curve
ESDS312 ESDS314 D006_TLP_Neg.gif
Figure 6. TLP I-V Curve, IO to GND Negative, tp=100 ns
ESDS312 ESDS314 D008_IEC_Neg.gif
Figure 8. -8 kV IEC 61000-4-2 Clamping Voltage Waveform
ESDS312 ESDS314 D010_Cap_Vbias.gif
Figure 10. Capacitance vs. Bias Voltage at 25°C
ESDS312 ESDS314 D012_S21.gif
Figure 12. Differential Insertion Loss