SPRSPB9B July   2025  – October 2025 F28E120SB , F28E120SC

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR and PWM X-BAR
      6. 5.4.6 GPIO and ADC Allocation
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Power Consumption Summary
      1. 6.4.1 System Current Consumption - Internal Supply
      2. 6.4.2 Operating Mode Test Description
      3. 6.4.3 Current Consumption Graphs
      4. 6.4.4 Reducing Current Consumption
    5. 6.5  Electrical Characteristics
    6. 6.6  Thermal Resistance Characteristics for PT Package
    7. 6.7  Thermal Resistance Characteristics for VFC Package
    8. 6.8  Thermal Resistance Characteristics for RHB Package
    9. 6.9  Thermal Design Considerations
    10. 6.10 System
      1. 6.10.1  Power Management Module (PMM)
        1. 6.10.1.1 Introduction
        2. 6.10.1.2 Overview
          1. 6.10.1.2.1 Power Rail Monitors
            1. 6.10.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.10.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
          2. 6.10.1.2.2 External Supervisor Usage
          3. 6.10.1.2.3 Delay Blocks
        3. 6.10.1.3 External Components
          1. 6.10.1.3.1 Decoupling Capacitors
            1. 6.10.1.3.1.1 VDDIO Decoupling
        4. 6.10.1.4 Power Sequencing
          1. 6.10.1.4.1 Supply Pins Ganging
          2. 6.10.1.4.2 Signal Pins Power Sequence
          3. 6.10.1.4.3 Supply Pins Power Sequence
            1. 6.10.1.4.3.1 Internal Power-Up Sequence
            2. 6.10.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 6.10.1.4.3.3 Supply Slew Rate
        5. 6.10.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.10.1.6 Power Management Module Electrical Data and Timing
          1. 6.10.1.6.1 Power Management Module Operating Conditions
          2. 6.10.1.6.2 Power Management Module Characteristics
      2. 6.10.2  Reset Timing
        1. 6.10.2.1 Reset Sources
        2. 6.10.2.2 Reset Electrical Data and Timing
          1. 6.10.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.10.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.10.2.2.3 Reset Timing Diagrams
      3. 6.10.3  Clock Specifications
        1. 6.10.3.1 Clock Sources
        2. 6.10.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.10.3.2.1.1 Input Clock Frequency
            2. 6.10.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.10.3.2.1.3 X1 Timing Requirements
            4. 6.10.3.2.1.4 PLL Characteristics
            5. 6.10.3.2.1.5 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            6. 6.10.3.2.1.6 Internal Clock Frequencies
        3. 6.10.3.3 Input Clocks and PLLs
        4. 6.10.3.4 XTAL Oscillator
          1. 6.10.3.4.1 Introduction
          2. 6.10.3.4.2 Overview
            1. 6.10.3.4.2.1 Electrical Oscillator
              1. 6.10.3.4.2.1.1 Modes of Operation
                1. 6.10.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.10.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.10.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.10.3.4.2.2 Quartz Crystal
          3. 6.10.3.4.3 Functional Operation
            1. 6.10.3.4.3.1 ESR – Effective Series Resistance
            2. 6.10.3.4.3.2 Rneg – Negative Resistance
            3. 6.10.3.4.3.3 Start-up Time
              1. 6.10.3.4.3.3.1 X1/X2 Precondition
            4. 6.10.3.4.3.4 DL – Drive Level
          4. 6.10.3.4.4 How to Choose a Crystal
          5. 6.10.3.4.5 Testing
          6. 6.10.3.4.6 Common Problems and Debug Tips
          7. 6.10.3.4.7 Crystal Oscillator Specifications
            1. 6.10.3.4.7.1 Crystal Oscillator Parameters
            2. 6.10.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.10.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.10.3.5 Internal Oscillators
          1. 6.10.3.5.1 System Oscillator SYSOSC
          2. 6.10.3.5.2 Wide Range Oscillator WROSC
      4. 6.10.4  Flash Parameters
        1. 6.10.4.1 Flash Parameters 
      5. 6.10.5  RAM Specifications
      6. 6.10.6  ROM Specifications
      7. 6.10.7  Emulation/JTAG
        1. 6.10.7.1 JTAG Electrical Data and Timing
          1. 6.10.7.1.1 JTAG Timing Requirements
          2. 6.10.7.1.2 JTAG Switching Characteristics
          3. 6.10.7.1.3 JTAG Timing Diagram
        2. 6.10.7.2 cJTAG Electrical Data and Timing
          1. 6.10.7.2.1 cJTAG Timing Requirements
          2. 6.10.7.2.2 cJTAG Switching Characteristics
          3. 6.10.7.2.3 cJTAG Timing Diagram
      8. 6.10.8  GPIO Electrical Data and Timing
        1. 6.10.8.1 GPIO – Output Timing
          1. 6.10.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.10.8.1.2 General-Purpose Output Timing Diagram
        2. 6.10.8.2 GPIO – Input Timing
          1. 6.10.8.2.1 General-Purpose Input Timing Requirements
          2. 6.10.8.2.2 Sampling Mode
        3. 6.10.8.3 Sampling Window Width for Input Signals
      9. 6.10.9  Interrupts
        1. 6.10.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.10.9.1.1 External Interrupt Timing Requirements
          2. 6.10.9.1.2 External Interrupt Switching Characteristics
          3. 6.10.9.1.3 External Interrupt Timing
      10. 6.10.10 Low-Power Modes
        1. 6.10.10.1 Clock-Gating Low-Power Modes
        2. 6.10.10.2 Low-Power Mode Wake-up Timing
          1. 6.10.10.2.1 IDLE Mode Timing Requirements
          2. 6.10.10.2.2 IDLE Mode Switching Characteristics
          3. 6.10.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.10.10.2.4 STANDBY Mode Timing Requirements
          5. 6.10.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.10.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.10.10.2.7 HALT Mode Timing Requirements
          8. 6.10.10.2.8 HALT Mode Switching Characteristics
          9. 6.10.10.2.9 HALT Entry and Exit Timing Diagram
    11. 6.11 Analog Peripherals
      1. 6.11.1 Analog Pins and Internal Connections
      2. 6.11.2 Analog-to-Digital Converter (ADC)
        1. 6.11.2.1 ADC Configurability
          1. 6.11.2.1.1 Signal Mode
        2. 6.11.2.2 ADC Electrical Data and Timing
          1. 6.11.2.2.1 ADC Operating Conditions
          2. 6.11.2.2.2 ADC Characteristics
          3. 6.11.2.2.3 ADC INL and DNL
          4. 6.11.2.2.4 ADC Performance Per Pin
          5. 6.11.2.2.5 ADC Input Model
          6. 6.11.2.2.6 ADC Timing Diagrams
      3. 6.11.3 Comparator Subsystem (CMPSS_LITE)
        1. 6.11.3.1 COMPDACOUT
        2. 6.11.3.2 CMPSS Connectivity Diagram
        3. 6.11.3.3 Block Diagram
        4. 6.11.3.4 CMPSS Electrical Data and Timing
          1. 6.11.3.4.1 CMPSS_LITE Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.11.3.4.2 CMPSS_LITE DAC Static Electrical Characteristics
          4. 6.11.3.4.3 CMPSS Illustrative Graphs
          5. 6.11.3.4.4 Buffered Output from CMPx_LITE_DACL Operating Conditions
          6. 6.11.3.4.5 Buffered Output from CMPx_LITE_DACL Electrical Characteristics
      4. 6.11.4 Programmable Gain Amplifier (PGA)
        1. 6.11.4.1 PGA Electrical Data and Timing
          1. 6.11.4.1.1 PGA Operating Conditions
          2. 6.11.4.1.2 PGA Characteristics
      5. 6.11.5 Temperature Sensor
        1. 6.11.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.11.5.1.1 Temperature Sensor Characteristics
    12. 6.12 Control Peripherals
      1. 6.12.1 Multichannel Pulse Width Modulator (MCPWM)
        1. 6.12.1.1 Control Peripherals Synchronization
        2. 6.12.1.2 MCPWM Electrical Data and Timing
          1. 6.12.1.2.1 MCPWM Timing Requirements
          2. 6.12.1.2.2 MCPWM Switching Characteristics
          3. 6.12.1.2.3 Trip-Zone Input Timing
            1. 6.12.1.2.3.1 PWM Hi-Z Characteristics Timing Diagram
      2. 6.12.2 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.12.2.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.12.2.2 ADCSOCAO or ADCSOCBO Timing Diagram
      3. 6.12.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.12.3.1 eQEP Electrical Data and Timing
          1. 6.12.3.1.1 eQEP Timing Requirements
          2. 6.12.3.1.2 eQEP Switching Characteristics
      4. 6.12.4 Enhanced Capture (eCAP)
        1. 6.12.4.1 eCAP Block Diagram
        2. 6.12.4.2 eCAP Synchronization
        3. 6.12.4.3 eCAP Electrical Data and Timing
          1. 6.12.4.3.1 eCAP Switching Characteristics
    13. 6.13 Communications Peripherals
      1. 6.13.1 Inter-Integrated Circuit (I2C)
        1. 6.13.1.1 I2C Electrical Data and Timing
          1. 6.13.1.1.1 I2C Timing Requirements
          2. 6.13.1.1.2 I2C Switching Characteristics
          3. 6.13.1.1.3 I2C Timing Diagram
      2. 6.13.2 Universal Asynchronous Receiver-Transmitter (UART)
      3. 6.13.3 Serial Peripheral Interface (SPI)
        1. 6.13.3.1 SPI Controller Mode Timings
          1. 6.13.3.1.1 SPI Controller Mode Timing Requirements
          2. 6.13.3.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.13.3.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.13.3.1.4 SPI Controller Mode Timing Diagrams
        2. 6.13.3.2 SPI Peripheral Mode Timings
          1. 6.13.3.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.13.3.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.13.3.2.3 SPI Peripheral Mode Timing Diagrams
      4. 6.13.4 Serial Communications Interface (SCI)
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Memory
      1. 7.2.1 C28x Memory Map
        1. 7.2.1.1 Dedicated RAM (Mx RAM)
      2. 7.2.2 Flash Memory Map
      3. 7.2.3 Peripheral Registers Memory Map
    3. 7.3  Identification
    4. 7.4  C28x Processor
      1. 7.4.1 Floating-Point Unit (FPU)
    5. 7.5  Direct Memory Access (DMA)
    6. 7.6  Device Boot Modes
      1. 7.6.1 Device Boot Configurations
        1. 7.6.1.1 Configuring Boot Mode Pins
        2. 7.6.1.2 Configuring Boot Mode Table Options
      2. 7.6.2 GPIO Assignments
    7. 7.7  Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8  Watchdog
    9. 7.9  C28x Timers
    10. 7.10 Dual-Clock Comparator (DCC)
      1. 7.10.1 Features
      2. 7.10.2 Mapping of DCCx Clock Source Inputs
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Typical Application
      1. 8.1.1 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     TAPE AND REEL INFORMATION

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
  • PT|48
  • VFC|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.2 Digital Signals

Table 5-3 Digital Signals
SIGNAL NAME PIN TYPE DESCRIPTION GPIO 48 PT 32 VFC 32 RHB
ADCSOCAO O ADC Start of Conversion A for External ADC 8, 33, 228 4, 25 2 2
ADCSOCBO O ADC Start of Conversion B for External ADC 10, 32 32 20 20
EQEP1_A I eQEP-1 Input A 6, 10, 11, 18, 20, 24, 28, 35, 40, 224 2, 6, 27, 31, 33, 48 4, 14, 15, 19, 21, 32 4, 14, 15, 19, 21, 32
EQEP1_B I eQEP-1 Input B 7, 11, 16, 19, 21, 29, 33, 37, 41, 228 1, 4, 25, 26, 29, 34, 43 2, 14, 17, 22, 31 2, 14, 17, 22, 29, 31
EQEP1_INDEX I/O eQEP-1 Index 0, 9, 13, 17, 23, 29, 32, 39, 43, 242 1, 5, 23, 32, 36, 42 3, 20, 28, 31 3, 20, 24, 28, 31
EQEP1_STROBE I/O eQEP-1 Strobe 1, 4, 8, 12, 16, 22, 28, 30, 226 2, 4, 24, 26, 38, 41 2, 25, 27, 32 2, 25, 27, 32
ERRORSTS O Error Status Output. This signal requires an external pulldown. 24, 28, 29 1, 2, 27 15, 31, 32 15, 31, 32
GPIO0 I/O General-Purpose Input Output 0 0 42 28 28
GPIO1 I/O General-Purpose Input Output 1 1 41 27 27
GPIO2 I/O General-Purpose Input Output 2 2 40
GPIO3 I/O General-Purpose Input Output 3 3 39 26 26
GPIO4 I/O General-Purpose Input Output 4 4 38 25 25
GPIO5 I/O General-Purpose Input Output 5 5 47 30 30
GPIO6 I/O General-Purpose Input Output 6 6 48
GPIO7 I/O General-Purpose Input Output 7 7 43 29
GPIO8 I/O General-Purpose Input Output 8 8
GPIO9 I/O General-Purpose Input Output 9 9
GPIO10 I/O General-Purpose Input Output 10 10
GPIO11 I/O General-Purpose Input Output 11 11 14 14
GPIO12 I/O General-Purpose Input Output 12 12 24
GPIO13 I/O General-Purpose Input Output 13 13 23
GPIO16 I/O General-Purpose Input Output 16 16 26
GPIO17 I/O General-Purpose Input Output 17 17
GPIO18 I/O General-Purpose Input Output 18 18 33 21 21
GPIO19 I/O General-Purpose Input Output 19 19 34 22 22
GPIO20 I/O General-Purpose Input Output 20 20
GPIO21 I/O General-Purpose Input Output 21 21
GPIO22 I/O General-Purpose Input Output 22 22
GPIO23 I/O General-Purpose Input Output 23 23
GPIO24 I/O General-Purpose Input Output 24 24 27 15 15
GPIO28 I/O General-Purpose Input Output 28 28 2 32 32
GPIO29 I/O General-Purpose Input Output 29 29 1 31 31
GPIO30 I/O General-Purpose Input Output 30 30
GPIO32 I/O General-Purpose Input Output 32 32 32 20 20
GPIO33 I/O General-Purpose Input Output 33 33 25
GPIO35 I/O General-Purpose Input Output 35 35 31 19 19
GPIO37 I/O General-Purpose Input Output 37 37 29 17 17
GPIO39 I/O General-Purpose Input Output 39 39
GPIO40 I/O General-Purpose Input Output 40 40
GPIO41 I/O General-Purpose Input Output 41 41
GPIO43 I/O General-Purpose Input Output 43 43 36 24
GPIO45 I/O General-Purpose Input Output 45 45 45
GPIO46 I/O General-Purpose Input Output 46 46
GPIO224 I/O General-Purpose Input Output 224 224 6 4 4
GPIO226 I/O General-Purpose Input Output 226 226 4 2 2
GPIO227 I/O General-Purpose Input Output 227 227 20 13 13
GPIO228 I/O General-Purpose Input Output 228 228 4 2 2
GPIO230 I/O General-Purpose Input Output 230 230 21 13 13
GPIO242 I/O General-Purpose Input Output 242 242 5 3 3
GPIO243 I/O General-Purpose Input Output 243 243
I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock 1, 3, 4, 8, 9, 18, 20, 29, 33, 37, 43, 227 1, 20, 25, 29, 33, 36, 38, 39, 41 13, 17, 21, 25, 26, 27, 31 13, 17, 21, 24, 25, 26, 27, 31
I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data 0, 2, 5, 10, 19, 21, 28, 32, 35, 230 2, 21, 31, 32, 34, 40, 42, 47 13, 19, 20, 22, 28, 30, 32 13, 19, 20, 22, 28, 30, 32
MCPWM1_1A O MCPWM-1 Output 1A 0, 4, 30, 224 6, 38, 42 4, 25, 28 4, 25, 28
MCPWM1_1B O MCPWM-1 Output 1B 1, 5, 9, 226 4, 41, 47 2, 27, 30 2, 27, 30
MCPWM1_2A O MCPWM-1 Output 2A 2, 6, 7, 29, 41, 230, 242 1, 5, 21, 40, 43, 48 3, 13, 31 3, 13, 29, 31
MCPWM1_2B O MCPWM-1 Output 2B 3, 7, 10, 40, 227, 228 4, 20, 39, 43 2, 13, 26 2, 13, 26, 29
MCPWM1_3A O MCPWM-1 Output 3A 0, 4, 6, 227 20, 38, 42, 48 13, 25, 28 13, 25, 28
MCPWM1_3B O MCPWM-1 Output 3B 1, 5, 230 21, 41, 47 13, 27, 30 13, 27, 30
MCPWM3_1A O MCPWM-3 Output 1A 7, 12, 28, 41 2, 24, 43 32 29, 32
MCPWM3_1B O MCPWM-3 Output 1B 11, 13, 29 1, 23 14, 31 14, 31
OUTPUTXBAR1 O Output X-BAR Output 1 2, 24, 227 20, 27, 40 13, 15 13, 15
OUTPUTXBAR2 O Output X-BAR Output 2 3, 37, 242 5, 29, 39 3, 17, 26 3, 17, 26
OUTPUTXBAR3 O Output X-BAR Output 3 4, 5, 224 6, 38, 47 4, 25, 30 4, 25, 30
OUTPUTXBAR4 O Output X-BAR Output 4 1, 6, 33 25, 41, 48 27 27
OUTPUTXBAR5 O Output X-BAR Output 5 7, 28 2, 43 32 29, 32
OUTPUTXBAR6 O Output X-BAR Output 6 9, 29, 43 1, 36 31 24, 31
OUTPUTXBAR7 O Output X-BAR Output 7 0, 11, 16, 30 26, 42 14, 28 14, 28
OUTPUTXBAR8 O Output X-BAR Output 8 17, 28, 45 2, 45 32 32
SCIA_RX I SCI-A Receive Data 0, 3, 5, 9, 28, 35 2, 31, 39, 42, 47 19, 26, 28, 30, 32 19, 26, 28, 30, 32
SCIA_TX O SCI-A Transmit Data 1, 2, 7, 8, 16, 24, 29, 37 1, 26, 27, 29, 40, 41, 43 15, 17, 27, 31 15, 17, 27, 29, 31
SCIB_RX I SCI-B Receive Data 11, 13, 19, 23, 41 23, 34 14, 22 14, 22
SCIB_TX O SCI-B Transmit Data 9, 10, 12, 18, 22, 40 24, 33 21 21
SPIA_CLK I/O SPI-A Clock 3, 9, 12, 18, 28, 32, 41, 226 2, 4, 24, 32, 33, 39 2, 20, 21, 26, 32 2, 20, 21, 26, 32
SPIA_PICO I/O SPI-A Peripheral In, Controller Out (PICO) 2, 7, 8, 11, 16, 20, 24, 224 6, 26, 27, 40, 43 4, 14, 15 4, 14, 15, 29
SPIA_POCI I/O SPI-A Peripheral Out, Controller In (POCI) 1, 4, 5, 10, 13, 17, 21, 35, 45, 228 4, 23, 31, 38, 41, 45, 47 2, 19, 25, 27, 30 2, 19, 25, 27, 30
SPIA_PTE I/O SPI-A Peripheral Transmit Enable (PTE) 0, 5, 11, 19, 23, 24, 29, 37, 242 1, 5, 27, 29, 34, 42, 47 3, 14, 15, 17, 22, 28, 30, 31 3, 14, 15, 17, 22, 28, 30, 31
SYNCOUT O External MCPWM Synchronization Pulse 6, 37, 39 29, 48 17 17
TDI I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input. 35 31 19 19
TDO O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input. 37 29 17 17
UARTA_RX I UART-A Receive Data 21, 29, 32, 35, 226 1, 4, 31, 32 2, 19, 20, 31 2, 19, 20, 31
UARTA_TX O UART-A Transmit Data 20, 28, 33, 37, 43, 224 2, 6, 25, 29, 36 4, 17, 32 4, 17, 24, 32
X1 I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. 19 34 22 22
X2 I/O Crystal oscillator output. 18 33 21 21
XCLKOUT O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. 16, 18, 243 26, 33 21 21