SPRS825F October   2012  – June 2020 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
      1. Table 5-1 Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
      2. Table 5-2 Current Consumption at 125-MHz C28x SYSCLKOUT and 125-MHz M3SSCLK
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for ZWT Package (Revision 0 Silicon)
    7. 5.7  Thermal Resistance Characteristics for ZWT Package (Revision A Silicon)
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Power Sequencing
        1. Table 5-3 Reset (XRS) Timing Requirements
        2. Table 5-4 Reset (XRS) Switching Characteristics
        3. 5.9.1.1   Power Management and Supervisory Circuit Solutions
      2. 5.9.2 Clock Specifications
        1. 5.9.2.1 Changing the Frequency of the Main PLL
        2. 5.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
          1. Table 5-5  Input Clock Frequency
          2. Table 5-7  Crystal Oscillator Electrical Characteristics
          3. Table 5-8  X1 Timing Requirements - PLL Enabled
          4. Table 5-9  X1 Timing Requirements - PLL Disabled
          5. Table 5-10 XCLKIN Timing Requirements - PLL Enabled
          6. Table 5-11 XCLKIN Timing Requirements - PLL Disabled
          7. Table 5-12 PLL Lock Times
        3. 5.9.2.3 Output Clock Frequency and Switching Characteristics
          1. Table 5-13 Output Clock Frequency
          2. Table 5-14 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        4. 5.9.2.4 Internal Clock Frequencies
          1. Table 5-15 Internal Clock Frequencies (150-MHz Devices)
      3. 5.9.3 Timing Parameter Symbology
        1. 5.9.3.1 General Notes on Timing Parameters
        2. 5.9.3.2 Test Load Circuit
      4. 5.9.4 Flash Timing – Master Subsystem
        1. Table 5-16 Master Subsystem – Flash/OTP Endurance
        2. Table 5-17 Master Subsystem – Flash Parameters
        3. Table 5-18 Master Subsystem – Flash/OTP Access Timing
        4. Table 5-19 Master Subsystem – Flash Data Retention Duration
      5. 5.9.5 Flash Timing – Control Subsystem
        1. Table 5-21 Control Subsystem – Flash/OTP Endurance
        2. Table 5-22 Control Subsystem – Flash Parameters
        3. Table 5-23 Control Subsystem – Flash/OTP Access Timing
        4. Table 5-24 Control Subsystem – Flash Data Retention Duration
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO - Output Timing
          1. Table 5-26 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO - Input Timing
          1. Table 5-27 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
        4. 5.9.6.4 Low-Power Mode Wakeup Timing
          1. Table 5-28 IDLE Mode Timing Requirements
          2. Table 5-29 IDLE Mode Switching Characteristics
          3. Table 5-30 STANDBY Mode Timing Requirements
          4. Table 5-31 STANDBY Mode Switching Characteristics
          5. Table 5-32 HALT Mode Timing Requirements
          6. Table 5-33 HALT Mode Switching Characteristics
      7. 5.9.7 External Interrupt Electrical Data and Timing
        1. Table 5-34 External Interrupt Timing Requirements
        2. Table 5-35 External Interrupt Switching Characteristics
    10. 5.10 Analog and Shared Peripherals
      1. 5.10.1 Analog-to-Digital Converter
        1. 5.10.1.1 Sample Mode
        2. 5.10.1.2 Start-of-Conversion Triggers
        3. 5.10.1.3 Analog Inputs
        4. 5.10.1.4 ADC Result Registers and EOC Interrupts
        5. 5.10.1.5 ADC Electrical Data and Timing
          1. Table 5-36 ADC Electrical Characteristics
          2. Table 5-37 External ADC Start-of-Conversion Switching Characteristics
      2. 5.10.2 Comparator + DAC Units
        1. 5.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
          1. Table 5-38 Electrical Characteristics of the Comparator/DAC
      3. 5.10.3 Interprocessor Communications
      4. 5.10.4 External Peripheral Interface
        1. 5.10.4.1 EPI General-Purpose Mode
        2. 5.10.4.2 EPI SDRAM Mode
        3. 5.10.4.3 EPI Host Bus Mode
          1. 5.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 5.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 5.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 5.10.4.3.1.3 HB-8 FIFO Mode
          2. 5.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 5.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 5.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 5.10.4.3.2.3 HB-16 FIFO Mode
        4. 5.10.4.4 EPI Electrical Data and Timing
          1. Table 5-52 EPI SDRAM Interface Switching Characteristics (see , , and )
          2. Table 5-53 EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics (see , , , and )
          3. Table 5-54 EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements (see and )
          4. Table 5-55 EPI General-Purpose Interface Switching Characteristics (see )
          5. Table 5-56 EPI General-Purpose Interface Timing Requirements (see and )
    11. 5.11 Master Subsystem Peripherals
      1. 5.11.1 Synchronous Serial Interface
        1. 5.11.1.1 Bit Rate Generation
        2. 5.11.1.2 Transmit FIFO
        3. 5.11.1.3 Receive FIFO
        4. 5.11.1.4 Interrupts
        5. 5.11.1.5 Frame Formats
      2. 5.11.2 Universal Asynchronous Receiver/Transmitter
        1. 5.11.2.1 Baud-Rate Generation
        2. 5.11.2.2 Transmit and Receive Logic
        3. 5.11.2.3 Data Transmission and Reception
        4. 5.11.2.4 Interrupts
      3. 5.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 5.11.3.1 Functional Overview
        2. 5.11.3.2 Available Speed Modes
        3. 5.11.3.3 I2C Electrical Data and Timing
          1. Table 5-57 I2C Timing
      4. 5.11.4 Cortex-M3 Controller Area Network
        1. 5.11.4.1 Functional Overview
      5. 5.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 5.11.5.1 Functional Description
      6. 5.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 5.11.6.1 Functional Overview
        2. 5.11.6.2 MII Signals
        3. 5.11.6.3 EMAC Electrical Data and Timing
          1. Table 5-59 Timing Requirements for MIITXCK (see )
          2. Table 5-60 Timing Requirements for MIIRXCK (see )
          3. Table 5-61 Switching Characteristics for EMAC MII Transmit (see )
          4. Table 5-62 Timing Requirements for EMAC MII Receive (see )
        4. 5.11.6.4 MDIO Electrical Data and Timing
          1. Table 5-63 Switching Characteristics for MDIO_CK (see )
          2. Table 5-64 Switching Characteristics for MDIO as Output (see )
          3. Table 5-65 Timing Requirements for MDIO as Input (see )
    12. 5.12 Control Subsystem Peripherals
      1. 5.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 5.12.1.1 HRPWM Electrical Data and Timing
          1. Table 5-66 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
        2. 5.12.1.2 ePWM Electrical Data and Timing
          1. Table 5-67 ePWM Timing Requirements
          2. Table 5-68 ePWM Switching Characteristics
          3. 5.12.1.2.1 Trip-Zone Input Timing
            1. Table 5-69 Trip-Zone Input Timing Requirements
      2. 5.12.2 Enhanced Capture Module
        1. 5.12.2.1 eCAP Electrical Data and Timing
          1. Table 5-70 eCAP Timing Requirement
          2. Table 5-71 eCAP Switching Characteristics
      3. 5.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 5.12.3.1 eQEP Electrical Data and Timing
          1. Table 5-72 eQEP Timing Requirements
          2. Table 5-73 eQEP Switching Characteristics
      4. 5.12.4 C28x Inter-Integrated Circuit Module
        1. 5.12.4.1 Functional Overview
        2. 5.12.4.2 Clock Generation
        3. 5.12.4.3 I2C Electrical Data and Timing
          1. Table 5-74 I2C Timing
      5. 5.12.5 C28x Serial Communications Interface
        1. 5.12.5.1 Architecture
        2. 5.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 5.12.6 C28x Serial Peripheral Interface
        1. 5.12.6.1 Functional Overview
        2. 5.12.6.2 SPI Electrical Data and Timing
          1. 5.12.6.2.1 Master Mode Timing
            1. Table 5-75 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-76 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.12.6.2.2 Slave Mode Timing
            1. Table 5-77 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-78 SPI Slave Mode External Timing (Clock Phase = 1)
      7. 5.12.7 C28x Multichannel Buffered Serial Port
        1. 5.12.7.1 McBSP Electrical Data and Timing
          1. 5.12.7.1.1 McBSP Transmit and Receive Timing
            1. Table 5-79 McBSP Timing Requirements
            2. Table 5-80 McBSP Switching Characteristics
          2. 5.12.7.1.2 McBSP as SPI Master or Slave Timing
            1. Table 5-81 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-82 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-83 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-84 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-85 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-86 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-87 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-88 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
  6. 6Detailed Description
    1. 6.1  Memory Maps
      1. 6.1.1 Control Subsystem Memory Map
      2. 6.1.2 Master Subsystem Memory Map
    2. 6.2  Identification
    3. 6.3  Master Subsystem
      1. 6.3.1 Cortex-M3 CPU
      2. 6.3.2 Cortex-M3 DMA and NVIC
      3. 6.3.3 Cortex-M3 Interrupts
      4. 6.3.4 Cortex-M3 Vector Table
      5. 6.3.5 Cortex-M3 Local Peripherals
      6. 6.3.6 Cortex-M3 Local Memory
      7. 6.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 6.4  Control Subsystem
      1. 6.4.1 C28x CPU/FPU/VCU
      2. 6.4.2 C28x Core Hardware Built-In Self-Test
      3. 6.4.3 C28x Peripheral Interrupt Expansion
      4. 6.4.4 C28x Direct Memory Access
      5. 6.4.5 C28x Local Peripherals
      6. 6.4.6 C28x Local Memory
      7. 6.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 6.5  Analog Subsystem
      1. 6.5.1 ADC1
      2. 6.5.2 ADC2
      3. 6.5.3 Analog Comparator + DAC
      4. 6.5.4 Analog Common Interface Bus
    6. 6.6  Master Subsystem NMIs
    7. 6.7  Control Subsystem NMIs
    8. 6.8  Resets
      1. 6.8.1 Cortex-M3 Resets
      2. 6.8.2 C28x Resets
      3. 6.8.3 Analog Subsystem and Shared Resources Resets
      4. 6.8.4 Device Boot Sequence
    9. 6.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 6.9.1 Analog Subsystem: Internal 1.8-V VREG
      2. 6.9.2 Digital Subsystem: Internal 1.2-V VREG
      3. 6.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
      4. 6.9.4 Connecting ARS and XRS Pins
    10. 6.10 Input Clocks and PLLs
      1. 6.10.1 Internal Oscillator (Zero-Pin)
      2. 6.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 6.10.3 External Oscillators (Pins X1, VSSOSC, XCLKIN)
      4. 6.10.4 Main PLL
      5. 6.10.5 USB PLL
    11. 6.11 Master Subsystem Clocking
      1. 6.11.1 Cortex-M3 Run Mode
      2. 6.11.2 Cortex-M3 Sleep Mode
      3. 6.11.3 Cortex-M3 Deep Sleep Mode
    12. 6.12 Control Subsystem Clocking
      1. 6.12.1 C28x Normal Mode
      2. 6.12.2 C28x IDLE Mode
      3. 6.12.3 C28x STANDBY Mode
    13. 6.13 Analog Subsystem Clocking
    14. 6.14 Shared Resources Clocking
    15. 6.15 Loss of Input Clock (NMI Watchdog Function)
    16. 6.16 GPIOs and Other Pins
      1. 6.16.1 GPIO_MUX1
      2. 6.16.2 GPIO_MUX2
      3. 6.16.3 AIO_MUX1
      4. 6.16.4 AIO_MUX2
    17. 6.17 Emulation/JTAG
    18. 6.18 Code Security Module
      1. 6.18.1 Functional Description
    19. 6.19 µCRC Module
      1. 6.19.1 Functional Description
      2. 6.19.2 CRC Polynomials
      3. 6.19.3 CRC Calculation Procedure
      4. 6.19.4 CRC Calculation for Data Stored In Secure Memory
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

GPIO_MUX1

One-hundred and thirty-six pins of the GPIO_MUX1 block can be selectively mapped through corresponding sets of registers to all Cortex-M3 peripherals, to all C28x peripherals, to 136General-Purpose Inputs, to 136 General-Purpose Outputs, or a mixture of all of the above. The first 64 pins of GPIO_MUX1 (GPIO0–GPIO63) can also be mapped to 12 ePWM Trip Inputs, 6 eCAP inputs, 3 External Interrupts to the C28x PIE, and the C28x STANDBY Mode Wakeup signal (LMPWAKE). Additionally, each GPIO_MUX1 pin can have a pullup enabled or disabled. By default, all pullups and outputs are disabled on reset, and all pins of the GPIO_MUX1 block are mapped to Cortex-M3 peripherals (and not to C28x peripherals).

Figure 6-15 shows the internal structure of GPIO_MUX1. The blue blocks represent the Master Subsystem side of GPIO_MUX1, and the green blocks are the Control Subsystem side. The grey block in the center, Pin-Level Mux, is where the GPIO_MUX1 pins are individually assigned between the two subsystems, based on how the configuration registers are programmed in the blue and green blocks (see Figure 6-16 for the configuration registers).

Pin-Level Mux assigns Master Subsystem peripheral signals, Control Subsystem peripheral signals, or GPIOs to the 136 GPIO_MUX1 pins. In addition to connecting peripheral I/Os of the two subsystems to pins, the Pin-Level Mux also provides other signals to the subsystems: XCLKIN and GPIO[S:A] IRQ signals to the Master Subsystem, plus GPTRIP[12:1] and GPI[63:0] signals to the Control Subsystem. XCLKIN carries a clock from an external pin to USB PLL and CAN modules. The 17 GPIO[S:A] IRQ signals are interrupt requests from selected external pins to the NVIC interrupt controller. The 12 GPTRIP[12:1] signals carry trip events from selected external pins to C28x control peripherals—ePWM, eCAP, and eQEP. Sixty-four GPI signals go to the C28x LPM GPIO Select block where one of them can be selected to wake up the C28x CPU from Low-Power Mode. One-hundred and thirty-six (136) GPI signals go to the C28x QUAL block where they can be configured with a qualification sampling period (see Figure 6-16).

The configuration registers for the muxing of Master Subsystem peripherals are organized in 17 sets (A–S), with each set being responsible for eight pins. The first nine sets of these registers (A–J) are programmable by the Cortex-M3 CPU through the AHB bus or the APB bus. The remaining sets of registers (K–S) are programmable by the AHB bus only. The configuration register for the muxing of Control Subsystem peripherals are organized in five sets (A–E), with each set being responsible for up to 32 pins. These registers are programmable by the C28x CPU through the C28x CPU bus. Figure 6-16 shows set A of the Master Subsystem GPIO configuration registers, set A of the Control Subsystem registers, and the muxing logic for one GPIO pin as driven by these registers.

F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2 gpio_prs820.gifFigure 6-14 GPIOs and Other Pins
F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2 gpio_mux1_all_pins_prs820.gifFigure 6-15 GPIO_MUX1 Block
F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2 gpio_mux1_one_pin_prs820.gifFigure 6-16 GPIO_MUX1 Pin Mapping Through Register Set A

For each of the 8 pins in set A of the Cortex-M3 GPIO registers, register GPIOPCTL selects between 1 of 11 possible primary Cortex-M3 peripheral signals, or 1 of 4 possible alternate peripheral signals. Register GPIOAPSEL then picks one output to propagate further along the muxing chain towards a given pin. The input takes the reverse path. See Table 6-27 and Table 6-28 for the mapping of Cortex-M3 peripheral signals to GPIO_MUX1 pins.

Similarly, on the C28x side, GPAMUX1 and GPAMUX2 registers select 1 of 4 possible C28x peripheral signals for each of 32 pins of set A. The selected C28x peripheral output then propagates further along the muxing chain towards a given pin. The input takes the reverse path. See Table 6-29 for the mapping of C28x peripheral signals to GPIO_MUX1 pins.

In addition to passing mostly digital signals, four GPIO_MUX1 pins can also be assigned to analog signals. The GPIO Analog Mode Select (GPIOAMSEL) Register is used to assign four pins to analog USB signals. PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes USB0DP, and PG6_GPIO46 becomes USB0ID. When analog mode is selected, these four pins are not available for digital GPIO_MUX1 options as described above.

Another special case is the External Oscillator Input signal (XCLKIN). This signal, available through pin PJ7_GPIO63, is directly tied to USBPLLCLK (clock input to USB PLL) and two CAN modules. XCLKIN is always available at these modules where it can be selected through local registers.

NOTE

For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is available on silicon revision 0 devices (GPIO and other functions listed in Table 4-1 are not available).

Table 6-27 GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1)

ANALOG
MODE
(USB PINS)
DEVICE
PIN NAME
M3
PRIMARY
MODE 1
M3
PRIMARY
MODE 2
M3
PRIMARY
MODE 3
M3
PRIMARY
MODE 4
M3
PRIMARY
MODE 5
M3
PRIMARY
MODE 6
M3
PRIMARY
MODE 7
M3
PRIMARY
MODE 8
M3
PRIMARY
MODE 9
M3
PRIMARY
MODE 10
M3
PRIMARY
MODE 11
PA0_GPIO0 U0RX I2C1SCL U1RX
PA1_GPIO1 U0TX I2C1SDA U1TX
PA2_GPIO2 SSI0CLK MIITXD2
PA3_GPIO3 SSI0FSS MIITXD1
PA4_GPIO4 SSI0RX MIITXD0 CAN0RX
PA5_GPIO5 SSI0TX MIIRXDV CAN0TX
PA6_GPIO6 I2C1SCL CCP1 MIIRXCK CAN0RX USB0EPEN
PA7_GPIO7 I2C1SDA CCP4 MIIRXER CAN0TX CCP3 USB0PFLT
PB0_GPIO8 CCP0 U1RX
PB1_GPIO9 CCP2 CCP1 U1TX
PB2_GPIO10 I2C0SCL CCP3 CCP0 USB0EPEN
PB3_GPIO11 I2C0SDA USB0PFLT
PB4_GPIO12 U2RX CAN0RX U1RX EPI0S23
PB5_GPIO13 CCP5 CCP6 CCP0 CAN0TX CCP2 U1TX EPI0S22
PB6_GPIO14 CCP1 CCP7 CCP5 EPI0S37(2)
PB7_GPIO15 EXTNMI MIIRXD1 EPI0S36(2)
PD0_GPIO16 CAN0RX U2RX U1RX CCP6 MIIRXDV
PD1_GPIO17 CAN0TX U2TX U1TX CCP7 MIITXER CCP2
PD2_GPIO18 U1RX CCP6 CCP5 EPI0S20
PD3_GPIO19 U1TX CCP7 CCP0 EPI0S21
PD4_GPIO20 CCP0 CCP3 MIITXD3 EPI0S19
PD5_GPIO21 CCP2 CCP4 MIITXD2 U2RX EPI0S28
PD6_GPIO22 MIITXD1 U2TX EPI0S29
PD7_GPIO23 CCP1 MIITXD0 EPI0S30
PE0_GPIO24 SSI1CLK CCP3 EPI0S8 USB0PFLT
PE1_GPIO25 SSI1FSS CCP2 CCP6 EPI0S9
PE2_GPIO26 CCP4 SSI1RX CCP2 EPI0S24
PE3_GPIO27 CCP1 SSI1TX CCP7 EPI0S25
PE4_GPIO28 CCP3 U2TX CCP2 MIIRXD0 EPI0S34(2)
PE5_GPIO29 CCP5 EPI0S35(2)
PE6_GPIO30
PE7_GPIO31
PF0_GPIO32 CAN1RX MIIRXCK
PF1_GPIO33 CAN1TX MIIRXER CCP3
PF2_GPIO34 MIIPHYINTR EPI0S32(2) SSI1CLK
PF3_GPIO35 MIIMDC EPI0S33(2) SSI1FSS
PF4_GPIO36 CCP0 MIIMDIO EPI0S12 SSI1RX
PF5_GPIO37 CCP2 MIIRXD3 EPI0S15 SSI1TX
USB0VBUS PF6_GPIO38 CCP1 MIIRXD2 EPI0S38(2)
PF7_GPIO39
PG0_GPIO40 U2RX I2C1SCL USB0EPEN EPI0S13
PG1_GPIO41 U2TX I2C1SDA EPI0S14
USB0DM PG2_GPIO42 MIICOL EPI0S39(2)
PG3_GPIO43 MIICRS
PG4_GPIO44
USB0DP PG5_GPIO45 CCP5 MIITXEN EPI0S40(2)
USB0ID PG6_GPIO46 MIITXCK EPI0S41(2)
PG7_GPIO47 MIITXER CCP5 EPI0S31
PH0_GPIO48 CCP6 MIIPHYRST EPI0S6
PH1_GPIO49 CCP7 EPI0S7
PH2_GPIO50 EPI0S1 MIITXD3
PH3_GPIO51 USB0EPEN EPI0S0 MIITXD2
PH4_GPIO52 USB0PFLT EPI0S10 MIITXD1 SSI1CLK
PH5_GPIO53 EPI0S11 MIITXD0 SSI1FSS
PH6_GPIO54 EPI0S26 MIIRXDV SSI1RX
PH7_GPIO55 MIIRXCK EPI0S27 SSI1TX
PJ0_GPIO56 MIIRXER EPI0S16 I2C1SCL
PJ1_GPIO57 EPI0S17 USB0PFLT I2C1SDA
PJ2_GPIO58 EPI0S18 CCP0
PJ3_GPIO59 EPI0S19 CCP6
PJ4_GPIO60 EPI0S28 CCP4
PJ5_GPIO61 EPI0S29 CCP2
PJ6_GPIO62 EPI0S30 CCP1
PJ7_GPIO63/
XCLKIN
CCP0
PC0_GPIO64 EPI0S32(2)
PC1_GPIO65 EPI0S33(2)
PC2_GPIO66 EPI0S37(2)
PC3_GPIO67 EPI0S36(2)
PC4_GPIO68 CCP5 MIITXD3 CCP2 CCP4 EPI0S2 CCP1
PC5_GPIO69 CCP1 CCP3 USB0EPEN EPI0S3
PC6_GPIO70 CCP3 U1RX CCP0 USB0PFLT EPI0S4
PC7_GPIO71 CCP4 CCP0 U1TX USB0PFLT EPI0S5
Blank fields represent Reserved functions.
This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.

Table 6-28 GPIO_MUX1 Pin Assignments (M3 Alternate Modes)(1)

ANALOG MODE
(USB PINS)
DEVICE PIN NAME M3
ALTERNATE
MODE 12
M3
ALTERNATE
MODE 13
M3
ALTERNATE
MODE 14
M3
ALTERNATE
MODE 15
PA0_GPIO0
PA1_GPIO1 SSI1FSS
PA2_GPIO2
PA3_GPIO3 SSI1CLK
PA4_GPIO4
PA5_GPIO5
PA6_GPIO6
PA7_GPIO7 MIIRXD1
PB0_GPIO8 SSI2TX CAN1TX U4TX
PB1_GPIO9 SSI2RX
PB2_GPIO10 SSI2CLK CAN1RX U4RX
PB3_GPIO11 SSI2FSS U1RX
PB4_GPIO12 CAN1TX SSI1TX
PB5_GPIO13 CAN1RX SSI1RX
PB6_GPIO14 MIICRS I2C0SDA U1TX SSI1CLK
PB7_GPIO15 I2C0SCL U1RX SSI1FSS
PD0_GPIO16 MIIRXD2 SSI0TX CAN1TX USB0EPEN
PD1_GPIO17 MIICOL SSI0RX CAN1RX USB0PFLT
PD2_GPIO18 SSI0CLK U1TX CAN0RX
PD3_GPIO19 SSI0FSS U1RX CAN0TX
PD4_GPIO20 U3TX CAN1TX
PD5_GPIO21 U3RX CAN1RX
PD6_GPIO22 I2C1SDA U1TX
PD7_GPIO23 I2C1SCL U1RX
PE0_GPIO24 SSI3TX CAN0RX SSI1TX
PE1_GPIO25 SSI3RX CAN0TX SSI1RX
PE2_GPIO26 SSI3CLK U2RX SSI1CLK
PE3_GPIO27 SSI3FSS U2TX SSI1FSS
PE4_GPIO28 U0RX EPI0S38(2) USB0EPEN
PE5_GPIO29 MIITXER U0TX USB0PFLT
PE6_GPIO30 MIIMDIO CAN0RX
PE7_GPIO31 MIIRXD3 CAN0TX
PF0_GPIO32 I2C0SDA TRACED2
PF1_GPIO33 I2C0SCL TRACED3
PF2_GPIO34 TRACECLK XCLKOUT
PF3_GPIO35 U0TX TRACED0
PF4_GPIO36 U0RX
PF5_GPIO37 MIITXEN
USB0VBUS PF6_GPIO38
PF7_GPIO39 CAN1TX
PG0_GPIO40 MIIRXD2 U4RX MIITXCK
PG1_GPIO41 MIIRXD1 U4TX MIITXER
USB0DM PG2_GPIO42
PG3_GPIO43 MIIRXDV TRACED1
PG4_GPIO44 CAN1RX
USB0DP PG5_GPIO45
USB0ID PG6_GPIO46
PG7_GPIO47 MIICRS
PH0_GPIO48 SSI3TX MIITXD3
PH1_GPIO49 MIIRXD0 SSI3RX MIITXD2
PH2_GPIO50 SSI3CLK MIITXD1
PH3_GPIO51 SSI3FSS MIITXD0
PH4_GPIO52 U3TX MIICOL
PH5_GPIO53 U3RX MIIPHYRST
PH6_GPIO54 MIITXEN SSI0TX MIIPHYINTR
PH7_GPIO55 MIITXCK SSI0RX MIIMDC
PJ0_GPIO56 SSI0CLK MIIMDIO
PJ1_GPIO57 MIIRXDV SSI0FSS MIIRXD3
PJ2_GPIO58 MIIRXCK SSI0CLK U0TX MIIRXD2
PJ3_GPIO59 MIIMDC SSI0FSS U0RX MIIRXD1
PJ4_GPIO60 MIICOL SSI1CLK MIIRXD0
PJ5_GPIO61 MIICRS SSI1FSS MIIRXDV
PJ6_GPIO62 MIIPHYINTR U2RX MIIRXER
PJ7_GPIO63/
XCLKIN
MIIPHYRST U2TX MIIRXCK
PC0_GPIO64 MIIRXD2
PC1_GPIO65 MIICOL
PC2_GPIO66 MIITXEN
PC3_GPIO67 MIITXCK
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PK0_GPIO72 SSI0TX
PK1_GPIO73 SSI0RX
PK2_GPIO74 SSI0CLK
PK3_GPIO75 SSI0FSS
PK4_GPIO76 MIITXEN SSI0TX
PK5_GPIO77 MIITXCK SSI0RX
PK6_GPIO78 MIITXER SSI0CLK
PK7_GPIO79 MIICRS SSI0FSS
PL0_GPIO80 MIIRXD3 SSI1TX
PL1_GPIO81 MIIRXD2 SSI1RX
PL2_GPIO82 MIIRXD1 SSI1CLK
PL3_GPIO83 MIIRXD0 SSI1FSS
PL4_GPIO84 MIICOL SSI3TX
PL5_GPIO85 MIIPHYRST SSI3RX
PL6_GPIO86 MIIPHYINTR SSI3CLK
PL7_GPIO87 MIIMDC SSI3FSS
PM0_GPIO88 MIIMDIO SSI2TX
PM1_GPIO89 MIITXD3 SSI2RX
PM2_GPIO90 MIITXD2 SSI2CLK
PM3_GPIO91 MIITXD1 SSI2FSS
PM4_GPIO92 MIITXD0
PM5_GPIO93 MIIRXDV
PM6_GPIO94 MIIRXER
PM7_GPIO95 MIIRXCK
PN0_GPIO96 I2C0SCL
PN1_GPIO97 I2C0SDA
PN2_GPIO98 U1RX
PN3_GPIO99 U1TX
PN4_GPIO100 U3TX
PN5_GPIO101 U3RX
PN6_GPIO102 U4RX EPI0S42(2) USB0EPEN
PN7_GPIO103 U4TX EPI0S43(2) USB0PFLT
PP0_GPIO104 I2C1SCL
PP1_GPIO105 I2C1SDA
PP2_GPIO106 I2C0SCL
PP3_GPIO107 I2C0SDA
PP4_GPIO108 I2C1SCL
PP5_GPIO109 I2C1SDA
PP6_GPIO110
PP7_GPIO111
PQ0_GPIO112
PQ1_GPIO113
PQ2_GPIO114 U0RX
PQ3_GPIO115 U0TX
PQ4_GPIO116 SSI1TX
PQ5_GPIO117 SSI1RX
PQ6_GPIO118
PQ7_GPIO119
PR0_GPIO120 SSI3TX
PR1_GPIO121 SSI3RX
PR2_GPIO122 SSI3CLK
PR3_GPIO123 SSI3FSS
PR4_GPIO124
PR5_GPIO125
PR6_GPIO126
PR7_GPIO127
PS0_GPIO128
PS1_GPIO129
PS2_GPIO130
PS3_GPIO131
PS4_GPIO132
PS5_GPIO133
PS6_GPIO134
PS7_GPIO135
Blank fields represent Reserved functions.
This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.

Table 6-29 GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)(1)

ANALOG MODE
(USB PINS)
DEVICE PIN NAME C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
PA0_GPIO0 GPIO0 EPWM1A
PA1_GPIO1 GPIO1 EPWM1B ECAP6
PA2_GPIO2 GPIO2 EPWM2A
PA3_GPIO3 GPIO3 EPWM2B ECAP5
PA4_GPIO4 GPIO4 EPWM3A
PA5_GPIO5 GPIO5 EPWM3B MFSRA ECAP1
PA6_GPIO6 GPIO6 EPWM4A EPWMSYNCO
PA7_GPIO7 GPIO7 EPWM4B MCLKRA ECAP2
PB0_GPIO8 GPIO8 EPWM5A ADCSOCAO
PB1_GPIO9 GPIO9 EPWM5B ECAP3
PB2_GPIO10 GPIO10 EPWM6A ADCSOCBO
PB3_GPIO11 GPIO11 EPWM6B ECAP4
PB4_GPIO12 GPIO12 EPWM7A
PB5_GPIO13 GPIO13 EPWM7B
PB6_GPIO14 GPIO14 EPWM8A
PB7_GPIO15 GPIO15 EPWM8B
PD0_GPIO16 GPIO16 SPISIMOA
PD1_GPIO17 GPIO17 SPISOMIA
PD2_GPIO18 GPIO18 SPICLKA
PD3_GPIO19 GPIO19 SPISTEA
PD4_GPIO20 GPIO20 EQEP1A MDXA
PD5_GPIO21 GPIO21 EQEP1B MDRA
PD6_GPIO22 GPIO22 EQEP1S MCLKXA
PD7_GPIO23 GPIO23 EQEP1I MFSXA
PE0_GPIO24 GPIO24 ECAP1 EQEP2A
PE1_GPIO25 GPIO25 ECAP2 EQEP2B
PE2_GPIO26 GPIO26 ECAP3 EQEP2I
PE3_GPIO27 GPIO27 ECAP4 EQEP2S
PE4_GPIO28 GPIO28 SCIRXDA
PE5_GPIO29 GPIO29 SCITXDA
PE6_GPIO30 GPIO30 EPWM9A
PE7_GPIO31 GPIO31 EPWM9B
PF0_GPIO32 GPIO32 I2CASDA SCIRXDA ADCSOCAO
PF1_GPIO33 GPIO33 I2CASCL EPWMSYNCO ADCSOCBO
PF2_GPIO34 GPIO34 ECAP1 SCIRXDA XCLKOUT
PF3_GPIO35 GPIO35 SCITXDA
PF4_GPIO36 GPIO36 SCIRXDA
PF5_GPIO37 GPIO37 ECAP2
USB0VBUS PF6_GPIO38 GPIO38
PF7_GPIO39 GPIO39
PG0_GPIO40 GPIO40
PG1_GPIO41 GPIO41
USB0DM PG2_GPIO42 GPIO42
PG3_GPIO43 GPIO43
PG4_GPIO44 GPIO44
USB0DP PG5_GPIO45 GPIO45
USB0ID PG6_GPIO46 GPIO46
PG7_GPIO47 GPIO47
PH0_GPIO48 GPIO48 ECAP5
PH1_GPIO49 GPIO49 ECAP6
PH2_GPIO50 GPIO50 EQEP1A
PH3_GPIO51 GPIO51 EQEP1B
PH4_GPIO52 GPIO52 EQEP1S
PH5_GPIO53 GPIO53 EQEP1I
PH6_GPIO54 GPIO54 SPISIMOA EQEP3A
PH7_GPIO55 GPIO55 SPISOMIA EQEP3B
PJ0_GPIO56 GPIO56 SPICLKA EQEP3S
PJ1_GPIO57 GPIO57 SPISTEA EQEP3I
PJ2_GPIO58 GPIO58 MCLKRA EPWM7A
PJ3_GPIO59 GPIO59 MFSRA EPWM7B
PJ4_GPIO60 GPIO60 EPWM8A
PJ5_GPIO61 GPIO61 EPWM8B
PJ6_GPIO62 GPIO62 EPWM9A
PJ7_GPIO63/
XCLKIN
GPIO63 EPWM9B
PC0_GPIO64 GPIO64 EQEP1A EQEP2I
PC1_GPIO65 GPIO65 EQEP1B EQEP2S
PC2_GPIO66 GPIO66 EQEP1S EQEP2A
PC3_GPIO67 GPIO67 EQEP1I EQEP2B
PC4_GPIO68 GPIO68
PC5_GPIO69 GPIO69
PC6_GPIO70 GPIO70
PC7_GPIO71 GPIO71
PK0_GPIO72 GPIO72 SPISIMOA
PK1_GPIO73 GPIO73 SPISOMIA
PK2_GPIO74 GPIO74 SPICLKA
PK3_GPIO75 GPIO75 SPISTEA
PK4_GPIO76 GPIO76
PK5_GPIO77 GPIO77
PK6_GPIO78 GPIO78
PK7_GPIO79 GPIO79
PL0_GPIO80 GPIO80
PL1_GPIO81 GPIO81
PL2_GPIO82 GPIO82
PL3_GPIO83 GPIO83
PL4_GPIO84 GPIO84
PL5_GPIO85 GPIO85
PL6_GPIO86 GPIO86
PL7_GPIO87 GPIO87
PM0_GPIO88 GPIO88
PM1_GPIO89 GPIO89
PM2_GPIO90 GPIO90
PM3_GPIO91 GPIO91
PM4_GPIO92 GPIO92 MDXA
PM5_GPIO93 GPIO93 MDRA
PM6_GPIO94 GPIO94 MCLKXA
PM7_GPIO95 GPIO95 MFSXA
PN0_GPIO96 GPIO96 MCLKRA
PN1_GPIO97 GPIO97 MFSRA
PN2_GPIO98 GPIO98
PN3_GPIO99 GPIO99
PN4_GPIO100 GPIO100
PN5_GPIO101 GPIO101
PN6_GPIO102 GPIO102
PN7_GPIO103 GPIO103
PP0_GPIO104 GPIO104 I2CSDAA
PP1_GPIO105 GPIO105 I2CSCLA
PP2_GPIO106 GPIO106 EQEP1A
PP3_GPIO107 GPIO107 EQEP1B
PP4_GPIO108 GPIO108 EQEP1S
PP5_GPIO109 GPIO109 EQEP1I
PP6_GPIO110 GPIO110 EQEP2A EQEP3S
PP7_GPIO111 GPIO111 EQEP2B EQEP3I
PQ0_GPIO112 GPIO112 EQEP2I EQEP3A
PQ1_GPIO113 GPIO113 EQEP2S EQEP3B
PQ2_GPIO114 GPIO114
PQ3_GPIO115 GPIO115
PQ4_GPIO116 GPIO116
PQ5_GPIO117 GPIO117
PQ6_GPIO118 GPIO118 SCITXDA
PQ7_GPIO119 GPIO119 SCIRXDA
PR0_GPIO120 GPIO120
PR1_GPIO121 GPIO121
PR2_GPIO122 GPIO122
PR3_GPIO123 GPIO123
PR4_GPIO124 GPIO124 EPWM7A
PR5_GPIO125 GPIO125 EPWM7B
PR6_GPIO126 GPIO126 EPWM8A
PR7_GPIO127 GPIO127 EPWM8B
PS0_GPIO128 GPIO128 EPWM9A
PS1_GPIO129 GPIO129 EPWM9B
PS2_GPIO130 GPIO130 EPWM10A
PS3_GPIO131 GPIO131 EPWM10B
PS4_GPIO132 GPIO132 EPWM11A
PS5_GPIO133 GPIO133 EPWM11B
PS6_GPIO134 GPIO134 EPWM12A
PS7_GPIO135 GPIO135 EPWM12B
Blank fields represent Reserved functions.