SPRS825E October   2012  – December 2017 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for ZWT Package (Revision 0 Silicon)
    7. 5.7  Thermal Resistance Characteristics for ZWT Package (Revision A Silicon)
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Power Sequencing
        1. 5.9.1.1 Power Management and Supervisory Circuit Solutions
      2. 5.9.2 Clock Specifications
        1. 5.9.2.1 Changing the Frequency of the Main PLL
        2. 5.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
        3. 5.9.2.3 Output Clock Frequency and Switching Characteristics
        4. 5.9.2.4 Internal Clock Frequencies
      3. 5.9.3 Timing Parameter Symbology
        1. 5.9.3.1 General Notes on Timing Parameters
        2. 5.9.3.2 Test Load Circuit
      4. 5.9.4 Flash Timing - Master Subsystem
      5. 5.9.5 Flash Timing - Control Subsystem
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO - Output Timing
        2. 5.9.6.2 GPIO - Input Timing
        3. 5.9.6.3 Sampling Window Width for Input Signals
        4. 5.9.6.4 Low-Power Mode Wakeup Timing
      7. 5.9.7 External Interrupt Electrical Data and Timing
    10. 5.10 Analog and Shared Peripherals
      1. 5.10.1 Analog-to-Digital Converter
        1. 5.10.1.1 Sample Mode
        2. 5.10.1.2 Start-of-Conversion Triggers
        3. 5.10.1.3 Analog Inputs
        4. 5.10.1.4 ADC Result Registers and EOC Interrupts
        5. 5.10.1.5 ADC Electrical Data and Timing
      2. 5.10.2 Comparator + DAC Units
        1. 5.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
      3. 5.10.3 Interprocessor Communications
      4. 5.10.4 External Peripheral Interface
        1. 5.10.4.1 EPI General-Purpose Mode
        2. 5.10.4.2 EPI SDRAM Mode
        3. 5.10.4.3 EPI Host Bus Mode
          1. 5.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
            1. 5.10.4.3.1.1 HB-8 Muxed Address/Data Mode
            2. 5.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
            3. 5.10.4.3.1.3 HB-8 FIFO Mode
          2. 5.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
            1. 5.10.4.3.2.1 HB-16 Muxed Address/Data Mode
            2. 5.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
            3. 5.10.4.3.2.3 HB-16 FIFO Mode
        4. 5.10.4.4 EPI Electrical Data and Timing
    11. 5.11 Master Subsystem Peripherals
      1. 5.11.1 Synchronous Serial Interface
        1. 5.11.1.1 Bit Rate Generation
        2. 5.11.1.2 Transmit FIFO
        3. 5.11.1.3 Receive FIFO
        4. 5.11.1.4 Interrupts
        5. 5.11.1.5 Frame Formats
      2. 5.11.2 Universal Asynchronous Receiver/Transmitter
        1. 5.11.2.1 Baud-Rate Generation
        2. 5.11.2.2 Transmit and Receive Logic
        3. 5.11.2.3 Data Transmission and Reception
        4. 5.11.2.4 Interrupts
      3. 5.11.3 Cortex-M3 Inter-Integrated Circuit
        1. 5.11.3.1 Functional Overview
        2. 5.11.3.2 Available Speed Modes
        3. 5.11.3.3 I2C Electrical Data and Timing
      4. 5.11.4 Cortex-M3 Controller Area Network
        1. 5.11.4.1 Functional Overview
      5. 5.11.5 Cortex-M3 Universal Serial Bus Controller
        1. 5.11.5.1 Functional Description
      6. 5.11.6 Cortex-M3 Ethernet Media Access Controller
        1. 5.11.6.1 Functional Overview
        2. 5.11.6.2 MII Signals
        3. 5.11.6.3 EMAC Electrical Data and Timing
        4. 5.11.6.4 MDIO Electrical Data and Timing
    12. 5.12 Control Subsystem Peripherals
      1. 5.12.1 High-Resolution PWM and Enhanced PWM Modules
        1. 5.12.1.1 HRPWM Electrical Data and Timing
        2. 5.12.1.2 ePWM Electrical Data and Timing
          1. 5.12.1.2.1 Trip-Zone Input Timing
      2. 5.12.2 Enhanced Capture Module
        1. 5.12.2.1 eCAP Electrical Data and Timing
      3. 5.12.3 Enhanced Quadrature Encoder Pulse Module
        1. 5.12.3.1 eQEP Electrical Data and Timing
      4. 5.12.4 C28x Inter-Integrated Circuit Module
        1. 5.12.4.1 Functional Overview
        2. 5.12.4.2 Clock Generation
        3. 5.12.4.3 I2C Electrical Data and Timing
      5. 5.12.5 C28x Serial Communications Interface
        1. 5.12.5.1 Architecture
        2. 5.12.5.2 Multiprocessor and Asynchronous Communication Modes
      6. 5.12.6 C28x Serial Peripheral Interface
        1. 5.12.6.1 Functional Overview
        2. 5.12.6.2 SPI Electrical Data and Timing
          1. 5.12.6.2.1 Master Mode Timing
          2. 5.12.6.2.2 Slave Mode Timing
      7. 5.12.7 C28x Multichannel Buffered Serial Port
        1. 5.12.7.1 McBSP Electrical Data and Timing
          1. 5.12.7.1.1 McBSP Transmit and Receive Timing
          2. 5.12.7.1.2 McBSP as SPI Master or Slave Timing
  6. 6Detailed Description
    1. 6.1  Memory Maps
      1. 6.1.1 Control Subsystem Memory Map
      2. 6.1.2 Master Subsystem Memory Map
    2. 6.2  Identification
    3. 6.3  Master Subsystem
      1. 6.3.1 Cortex-M3 CPU
      2. 6.3.2 Cortex-M3 DMA and NVIC
      3. 6.3.3 Cortex-M3 Interrupts
      4. 6.3.4 Cortex-M3 Vector Table
      5. 6.3.5 Cortex-M3 Local Peripherals
      6. 6.3.6 Cortex-M3 Local Memory
      7. 6.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
    4. 6.4  Control Subsystem
      1. 6.4.1 C28x CPU/FPU/VCU
      2. 6.4.2 C28x Core Hardware Built-In Self-Test
      3. 6.4.3 C28x Peripheral Interrupt Expansion
      4. 6.4.4 C28x Direct Memory Access
      5. 6.4.5 C28x Local Peripherals
      6. 6.4.6 C28x Local Memory
      7. 6.4.7 C28x Accessing Shared Resources and Analog Peripherals
    5. 6.5  Analog Subsystem
      1. 6.5.1 ADC1
      2. 6.5.2 ADC2
      3. 6.5.3 Analog Comparator + DAC
      4. 6.5.4 Analog Common Interface Bus
    6. 6.6  Master Subsystem NMIs
    7. 6.7  Control Subsystem NMIs
    8. 6.8  Resets
      1. 6.8.1 Cortex-M3 Resets
      2. 6.8.2 C28x Resets
      3. 6.8.3 Analog Subsystem and Shared Resources Resets
      4. 6.8.4 Device Boot Sequence
    9. 6.9  Internal Voltage Regulation and Power-On-Reset Functionality
      1. 6.9.1 Analog Subsystem: Internal 1.8-V VREG
      2. 6.9.2 Digital Subsystem: Internal 1.2-V VREG
      3. 6.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
      4. 6.9.4 Connecting ARS and XRS Pins
    10. 6.10 Input Clocks and PLLs
      1. 6.10.1 Internal Oscillator (Zero-Pin)
      2. 6.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
      3. 6.10.3 External Oscillators (Pins X1, VSSOSC, XCLKIN)
      4. 6.10.4 Main PLL
      5. 6.10.5 USB PLL
    11. 6.11 Master Subsystem Clocking
      1. 6.11.1 Cortex-M3 Run Mode
      2. 6.11.2 Cortex-M3 Sleep Mode
      3. 6.11.3 Cortex-M3 Deep Sleep Mode
    12. 6.12 Control Subsystem Clocking
      1. 6.12.1 C28x Normal Mode
      2. 6.12.2 C28x IDLE Mode
      3. 6.12.3 C28x STANDBY Mode
    13. 6.13 Analog Subsystem Clocking
    14. 6.14 Shared Resources Clocking
    15. 6.15 Loss of Input Clock (NMI Watchdog Function)
    16. 6.16 GPIOs and Other Pins
      1. 6.16.1 GPIO_MUX1
      2. 6.16.2 GPIO_MUX2
      3. 6.16.3 AIO_MUX1
      4. 6.16.4 AIO_MUX2
    17. 6.17 Emulation/JTAG
    18. 6.18 Code Security Module
      1. 6.18.1 Functional Description
    19. 6.19 µCRC Module
      1. 6.19.1 Functional Description
      2. 6.19.2 CRC Polynomials
      3. 6.19.3 CRC Calculation Procedure
      4. 6.19.4 CRC Calculation for Data Stored In Secure Memory
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|289
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from October 29, 2015 to December 15, 2017 (from D Revision (October 2015) to E Revision)

  • Global: Removed Q temperature range (–40°C to 125°C).Go
  • Section 1.1 (Features): Updated Temperature Options. Go
  • Table 3-1 (Device Comparison): Changed "Flash (KB)" to "Flash (ECC) (KB)". Changed "RAM ECC (KB)" to "RAM (ECC) (KB)". Changed "RAM Parity (KB)" to "RAM (Parity) (KB)". Changed "IPC Message RAM Parity (KB)" to "IPC Message RAM (Parity) (KB)". Changed "Supplemental RAM Parity (KB)" to "Shared RAM (Parity) (KB)". Go
  • Table 3-1: Removed Q temperature range (–40°C to 125°C).Go
  • Section 3.1 (Related Products): Added section.Go
  • Table 4-1 (Signal Descriptions): Changed BOOT_3 to Bmode_pin4. Changed BOOT_2 to Bmode_pin3. Changed BOOT_1 to Bmode_pin2. Changed BOOT_0 to Bmode_pin1.Go
  • Section 5.2 (ESD Ratings): Updated section. Go
  • Section 5.3 (Recommended Operating Conditions): Removed Q temperature range (–40°C to 125°C). Go
  • Section 5.9.1 (Power Sequencing): Added "(for analog pins, this value is 0.7 V above VDDA)" to "There is no power sequencing requirement needed ..." paragraph. Go
  • Table 5-66 (High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)): Updated footnote. Go
  • Section 5.12.6 (C28x Serial Peripheral Interface): Updated "Rising edge with phase delay" clocking scheme.Go
  • Section 5.12.6.2.1 (Master Mode Timing): Updated section. Go
  • Section 5.12.6.2.2 (Slave Mode Timing): Updated section. Go
  • Table 6-13 (Device Identification Registers): Replaced "Device Revision Register" table with "Device Identification Registers" table. Go
  • Table 6-17 (Master Subsystem Boot Mode Selection): Changed BOOT_3 to Bmode_pin4. Changed BOOT_2 to Bmode_pin3. Changed BOOT_1 to Bmode_pin2. Changed BOOT_0 to Bmode_pin1.Go
  • Figure 6-10 (Cortex-M3 Clocks and Low-Power Modes): Updated "MAIN PLL" and "USB PLL" blocks.Go
  • Section 7 (Applications, Implementation, and Layout): Updated section. Go
  • Section 8 (Device and Documentation Support): Restructured and updated section. Go
  • Figure 8-1 (Device Nomenclature): Updated TEMPERATURE RANGE.Go
  • Section 8.2 (Tools and Software): Added "Models" section.Go
  • Section 8.3 (Documentation Support): Added An Introduction to IBIS (I/O Buffer Information Specification) Modeling Application Note. Go